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    • 10. 发明申请
    • PLL FOR SYNTHESIZING FREQUENCIES HAVING RATIONAL RELATIONSHIPS WITH A REFERENCE FREQUENCY
    • 用于合成具有参考频率的正则关系的频率的PLL
    • WO0191299A3
    • 2002-06-20
    • PCT/US0117240
    • 2001-05-24
    • BROADBAND INNOVATIONS INC
    • PETROVIC BRANISLAV AASHKENASI MAX
    • H03L7/08H03B21/02H03B21/04H03L7/16
    • H03B21/025H03B21/04H03L7/16
    • A single loop PLL frequency synthesizer, operates at comparison frequencies above 100 MHz, with excellent phase noise performance, but allows for small frequency steps lower than 10 kHz and is suitable for integration within ASICs. The output frequency and the reference clock frequency always have a rational relationship (i.e. the ratio of the two frequencies can always be represented as a ratio of two integer numbers). This ratio can always be expanded into various expressions of equivalent fraction expansions. The equivalent fractions take the form of a series of divided, added or subtracted terms, each term itself being a rational number. For each synthesized frequency, the computation of expansion terms yields specific, different values of the terms, with possibly multiple solutions. The realization in hardware of the computed fraction expansion terms is achieved by the means of a specific combination of frequency division and frequency translation of the reference clock frequency and/or of the oscillator frequency.
    • 单回路PLL频率合成器在100 MHz以上的比较频率下工作,具有出色的相位噪声性能,但允许低于10 kHz的小频率步长,适用于ASIC集成。 输出频率和参考时钟频率总是具有合理的关系(即,两个频率的比率总是可以表示为两个整数的比率)。 该比率可以总是扩展到等效分数扩展的各种表达式。 等价分数采取一系列分,加或减术语的形式,每个术语本身都是有理数。 对于每个合成频率,扩展项的计算产生具体的不同的术语值,可能具有多个解。 计算的分数扩展项的硬件实现是通过参考时钟频率和/或振荡器频率的分频和频率转换的特定组合来实现的。