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    • 1. 发明申请
    • PREDICTIVE FEEDBACK COMPENSATION FOR PWM SWITCHING AMPLIFIERS
    • PWM开关放大器的预测反馈补偿
    • WO2009142718A3
    • 2010-02-18
    • PCT/US2009003083
    • 2009-05-19
    • SILICON LAB INCBEALE RICHARD GKHOURY JOHN M
    • BEALE RICHARD GKHOURY JOHN M
    • H03F3/217
    • H03F3/217H03F3/2173
    • Methods and systems are disclosed for predictive feedback compensation (PFC) circuitry for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Closed loop width adjustment can also be applied by providing timing feedback signals associated with the pre-compensation of the PWM input signals. Traditional feedback techniques can also be used in conjunction with the predictive feedback compensation (PFC) circuitry.
    • 公开了用于通过基于电源电压预补偿PWM输入来抑制由脉冲宽度调制(PWM)开关放大器中的电源电压变化和输出幅度切换非理想性引起的失真的预测反馈补偿(PFC)电路的方法和系统, 输出脉冲幅度。 与先前PWM输出信号相关的输出幅度误差用于预测未来PWM输出信号预期的输出幅度误差。 这些预测的输出振幅误差然后用于调整未来PWM输出信号的脉冲宽度。 也可以通过提供与PWM输入信号的预补偿相关联的定时反馈信号来应用闭环宽度调整。 传统的反馈技术也可以与预测反馈补偿(PFC)电路结合使用。
    • 4. 发明申请
    • MICRO CONTROLLER UNIT (MCU) WITH RTC
    • 微控制器单元(MCU)与RTC
    • WO2006004973A3
    • 2006-12-28
    • PCT/US2005023407
    • 2005-06-29
    • SILICON LAB INCFERNALD KENNETH WALFANO E DONALD
    • FERNALD KENNETH WALFANO E DONALD
    • G06F1/26
    • G06F1/3203
    • A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand­alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.
    • 公开了具有独立实时时钟(RTC)的微控制器单元(MCU)。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。 主时钟电路为处理电路提供定时。 电源控制电路控制处理电路和主时钟电路的电源,以控制其操作至少在全功率模式下工作,从供电电压输入和低功耗模式绘制小于全功率模式 功率电平由电源电压输入。 还提供独立的RTC电路,独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。 由RTC时钟电路计时钟的定时器可操作地增加存储的时间值以便从其输出,RTC时钟电路具有确定的时基。 输入/输出(I / O)设备提供处理电路对定时器输出的结果的访问。 电源管理电路管理独立RTC电路的电源,使得RTC时钟电路,定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。
    • 8. 发明申请
    • DIGITALLY-SYNTHESIZED LOOP FILTER CIRCUIT PARTICULARLY USEFUL FOR A PHASE LOCKED LOOP
    • 数字合成环路滤波器电路特别适用于锁相环路
    • WO0205428A2
    • 2002-01-17
    • PCT/US0121644
    • 2001-07-10
    • SILICON LAB INC
    • PERROTT MICHAEL HBAIRD REX T
    • H03L7/085H03L7/087H03L7/091H03L7/093H03L7/095H04L7/00H04L7/033H03L
    • H04L7/033H03L7/085H03L7/087H03L7/091H03L7/093H03L7/095H04L7/0004
    • In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is "integrated" by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent "size" of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.
    • 在诸如PLL的反馈系统中,与环路滤波电容器相关联的积分功能被数字地实现,并且容易在与PLL相同的集成电路管芯上实现。 在一个优选实施例中,利用模拟相位检测器,其相位误差输出信号被ΔΣ调制以使用数字(即,离散时间和离散值)信号来编码相位误差的量值。 该数字相位误差信号由包括例如数字累加器的数字积分模块“集成”,该数字累加器的输出然后被转换为模拟信号,可选地与环路前馈信号组合,然后作为控制电压 到压控振荡器。 由数字积分模块提供的积分电容器功能的等效“尺寸”可以通过增加或减少数字模块内的电路的位分辨率来改变。