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1. 发明申请

WO2006037317A3 TWO-STEP OXIDATION PROCESS FOR SEMICONDUCTOR WAFERS 审中-公开
标题翻译：两级氧化法半导体DISCS
公开(公告)号：WO2006037317A3
公开(公告)日：2006-07-27
申请号：PCT/DE2005001790
申请日：2005-10-06
申请人： X FAB SEMICONDUCTOR FOUNDRIES , LERNER RALF , ECKOLDT UWE
发明人： LERNER RALF , ECKOLDT UWE
IPC分类号： H01L21/762
CPC分类号： H01L21/76202
摘要： The invention relates to an efficient method for the thermal oxidation of preferably silicon semiconductor wafers while using the LOCOS process (Local Oxidation Of Silicon). The mechanical stresses to which the wafers are subjected should be reduced. To this end, the invention provides an oxidation method involving the provision of a substrate (1) with a front side (12) that is to be structured and with a rear side (13). The substrate is oxidized in two steps. During a first step, the rear side (13) is covered with a layer (4) that inhibits an oxidation. During a second step of oxidation, the oxidation-inhibiting layer (4) no longer exists. During both steps, an oxide thickness (D10) greater than that on the rear side (13) results on the front side (12).
摘要翻译：它优选是硅晶片的热氧化，在LOGOS过程（局部氧化硅）的申请中所描述的有效方法。盘的机械应力应减少。提出了一种氧化方法具有提供具有前侧被结构化的（12）和后侧（13）的基板（1）的。有氧化分两步基板。在第一步骤中，背面（13）覆盖有氧化抑制层（4）。在第二步骤中，氧化作用，抗氧化层（4）不再存在。上的前侧（12），从而在两个步骤期间更大的氧化物厚度（D10）比在后侧（13）。

2. 发明申请

WO2004095567A8 MONITORING THE REDUCTION IN THICKNESS AS MATERIAL IS REMOVED FROM A WAFER COMPOSITE AND TEST STRUCTURE FOR MONITORING REMOVAL OF MATERIAL 审中-公开
标题翻译： CONTROL在厚度DISC复合的减少和测试结构用于去除控制
公开(公告)号：WO2004095567A8
公开(公告)日：2005-12-22
申请号：PCT/DE2004000801
申请日：2004-04-16
申请人： X FAB SEMICONDUCTOR FOUNDRIES , LERNER RALF
发明人： LERNER RALF
IPC分类号： H01L21/68 , H01L21/762 , H01L23/544
CPC分类号： H01L22/34 , H01L21/76229 , H01L21/76232
摘要： The aim of the invention is to create a simple monitoring or testing method for monitoring a reduction in thickness as material is removed from a bonded semiconductor wafer pair, which prevents failure effects as material is removed from wafers (polishing, grinding or lapping). In addition, the costs of the material removal process should be reduced by minimizing the complexity of monitoring, as well as by reducing the amount of resulting refuse. To this end, the invention provides a test structure (4, 5, 6, 7, 8, 9) comprised of a systematic row of a number of different depth trenches that are made in the (active) wafer (2). A thickness (h6; h7) of the active wafer (2) desired during material removal, particularly during a polishing, corresponds to the depth (t6; t7) of a reference trench (6; 7) of the trenches of the test structure, said reference trench (6) being surrounded by flatter and deeper trenches (5, 7). The active wafer (2), via the side (2a) on which the test structure was provided, is bonded to the second wafer of the semiconductor wafer pair provided as a supporting wafer (1). A removal of material, particularly a polishing, is effected on the rear (2b) of the active wafer (2) until the reference trench (6) is exposed. The result is visually observed (30) in order to monitor the reduction in thickness as material is removed from the first wafer (2).
摘要翻译：它是由一个键合晶片对，一个简单的控制或测试方法用于控制厚度的减小，这盘移除过程中减小误差的影响（抛光，研磨或研磨）来创建。去除工艺的成本也应通过减少检查如何得到委员会的成本降低。本发明公开的测试结构（4,5,6,7,8,9），由被导入到（活性）盘（2）一个系统的一系列的数，不同地深沟槽。 A中的移除期间，特别是抛光目标厚度的（H6，H7）说有源板（2）对应于深度（T6; T7）的参考沟槽（6; 7）的测试结构的沟槽，其从较浅的和较深的（6）引用沟槽的沟槽包围（5,7）。有源板（2）结合到所述测试结构的侧面（2a）中被放置在半导体磁盘对作为载体盘的第二盘（1）上。的消融，特别是从后方侧的抛光（2b）的所述有效平板（2），以暴露沟槽参考（6）制成。结果在视觉上，用于控制在所述第一盘（2）的厚度的减少观察到（30）。

3. 发明申请

WO2004095570A3 TEST STRUCTURE FOR ELECTRICALLY VERIFYING THE DEPTHS OF TRENCH-ETCHINGS IN AN SOI WAFER, AND ASSOCIATED WORKING METHODS 审中-公开
标题翻译： FOR的电检查槽的深度测试结构蚀刻在SOI晶片及相关业务
公开(公告)号：WO2004095570A3
公开(公告)日：2005-01-06
申请号：PCT/DE2004000815
申请日：2004-04-19
申请人： X FAB SEMICONDUCTOR FOUNDRIES , LERNER RALF
发明人： LERNER RALF
IPC分类号： H01L23/544 , H01L21/762
CPC分类号： H01L22/34
摘要： The aim of the invention is to discover a simple to implement and reliable recognition of the moment at which insulating trenches reach the buried insulating layer during an etching operation. The technological reliability during the etching of these trenches should be increased, the production of refuse should be prevented, and costs should be reduced. To these ends, the invention provides a test structure for verifying an insulating trench etching in an SOI wafer. After an etching of insulating trenches, this test structure has a row of connected islands, whereby each island is surrounded by a trench. This trench has a different width from island to island (A, B; B, C) while including a trench width that appears in the form of an insulating trench in an active circuit. A section of the surrounding trench (a, b) of each island (A, B) forms a common piece with the trench of adjacent islands. The respective section has, in the inner islands, the width of the adjacent trench having the next larger or next smaller measure of width in the row.
摘要翻译：一个易于使用的和可靠的检测的掩埋绝缘层上的隔离沟槽的通过蚀刻的时间寻求。这些沟槽刻蚀过程中的技术安全应增加，委员会避免，可以节省成本。公开了用于在一个SOI晶片，其中，所述测试结构隔离的蚀刻之后包括测试Isoliergrabenätzung的测试结构沟槽一系列连续的岛是由每个岛具有沟槽，该沟槽（从岛到岛A，B包围;乙是，不同宽度的C），包括 - 产生作为绝缘沟槽中的有源电路 - 严重宽度。周边沟槽的一部分（A，B）每个岛的（A，B）形成与相邻的岛的槽共同的部分。每个部分在其内的岛屿，沟槽的相邻行中的下一个更高或下更小的宽度尺寸的宽度。

4. 发明申请

WO2009016134A1 PRODUCTION OF ISOLATION TRENCHES WITH DIFFERENT SIDEWALL DOPINGS 审中-公开
标题翻译：与不同的侧面墙壁掺杂制造ISOLATIONSGRAEBEN
公开(公告)号：WO2009016134A1
公开(公告)日：2009-02-05
申请号：PCT/EP2008059835
申请日：2008-07-25
申请人： X FAB SEMICONDUCTOR FOUNDRIES , LERNER RALF
发明人： LERNER RALF
IPC分类号： H01L21/762
CPC分类号： H01L21/76264 , H01L21/743 , H01L21/76229 , H01L21/76237
摘要： A description is given of a method for producing isolation trenches (32, 34) with different sidewall dopings on a silicon-based substrate wafer for use in a trench-isolated smart power technology. In this case, a first trench (32) having a first width and a second trench (34) having a second width, which is greater than the first width, are formed using a hard mask (30). The sidewalls of the first and second trenches are doped in accordance with a first doping type in order to produce sidewalls having a first doping. A material layer (50, 51, 60, 51) is deposited with a thickness determined so as to fill the first trench (32) completely to beyond the hard mask and to maintain a gap (34a) in the second trench (34). By means of isotropic etching, the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench. A further doping of sidewalls of the first trench or of the second trench in the presence of the residual material is then performed.
摘要翻译：一种方法，用于生产具有用于在一个严重的隔离智能功率技术使用基于硅的衬底晶片上的不同侧壁的掺杂隔离沟槽（32，34）中进行了描述。在这种情况下，具有第一宽度和具有第二宽度比所述第一宽度大的第二沟槽（34）的第一沟槽（32），通过使用硬掩模（30）形成。有掺杂根据第一掺杂类型，用于产生第一掺杂的侧壁的第一和第二沟槽的侧壁。有材料（50，51，60，51），其厚度沉积，其被确定为所述第一沟槽（32）在硬掩模并进入第二沟槽（34），以完全填满保持间隙（34a的层）。材料层从第二沟槽除去，但保留与材料层的剩余材料在通过各向同性蚀刻第一沟槽。此后，所述第一沟槽和所述第二沟槽的侧壁的另外的掺杂中的残余材料的存在下进行。

5. 发明申请

WO2009000921A2 SEMICONDUCTOR STRUCTURE FOR THE PRODUCTION OF A CARRIER WAFER CONTACT IN A TRENCH-INSULATED SOI DISK 审中-公开
标题翻译：半导体结构用于生产TRAEGERWAFERKONTAKTES的沟槽INSULATED SOI DISK
公开(公告)号：WO2009000921A2
公开(公告)日：2008-12-31
申请号：PCT/EP2008058292
申请日：2008-06-27
申请人： X FAB SEMICONDUCTOR FOUNDRIES , LERNER RALF
发明人： LERNER RALF
CPC分类号： H01L21/84 , H01L21/743 , H01L21/76286 , H01L27/1203
摘要： The invention discloses a semiconductor structure for the production of a carrier wafer contact in trench-isolated SOI disks, wherein said semiconductor structure can be used as deep contact (7, 6, 30') to the carrier wafer (1) of a thick SOI disk and/or as trench isolation (40). For both structures, the same method steps are used for the use thereof as deep contact to the carrier wafer of the thick SOI disk and also as trench isolation.
摘要翻译：本发明提供一种半导体结构的制造在严重分离SOI晶片的载体晶片接触，无论是作为可使用深的接触（7,6，30“），以一个厚的SOI晶片的载体晶片（1）以及严重的绝缘（40）。在这种情况下来两种结构，使用相同的程序，这是用来既作为与厚的SOI晶片的载体晶片以及严重隔离深接触。

6. 发明申请

WO2006037313A3 METHOD FOR THE CONSTRUCTION OF VERTICAL POWER TRANSISTORS WITH DIFFERING POWERS BY COMBINATION OF PRE-DEFINED PART PIECES 审中-公开
标题翻译：法在施工提供不同的服务垂直功率晶体管的按组合PREDEFINED削减
公开(公告)号：WO2006037313A3
公开(公告)日：2006-10-26
申请号：PCT/DE2005001780
申请日：2005-10-05
申请人： X FAB SEMICONDUCTOR FOUNDRIES , ALPHA MICROELECTRONICS GMBH , LERNER RALF , MIESCH WOLFGANG
发明人： LERNER RALF , MIESCH WOLFGANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5072 , G06F17/5081
摘要： Method and system for designing a vertical MOS power transistor with specified design output. The method comprises the composition of a layout for the vertical MOS power transistor as a combination of at least partly different layout sections, each with known design data with at least one first layout section with a known number of individual transistors and the fixing of the specific design output by means of the known design data and the number of applied layout sections.
摘要翻译：方法和系统，用于设计具有特定的设计容量的垂直功率MOS晶体管。该方法包括组装垂直功率MOS晶体管的布局至少部分地不同的布局部分，每个部分具有与至少一个第一布局截面已知的设计数据的一个组合中，具有各个晶体管单元的预定数量，并通过公知的装置调节所述规定的设计功率设计数据，并用布局部件的数量。

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