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2. 发明申请

WO2007107795A3 DATA PROCESSING HARDWARE 审中-公开
标题翻译：数据处理硬件
公开(公告)号：WO2007107795A3
公开(公告)日：2008-04-17
申请号：PCT/GB2007050141
申请日：2007-03-21
申请人： CAMBRIDGE DISPLAY TECH , SMITH EUAN CHRISTOPHER , LAWRENCE NICHOLAS
发明人： SMITH EUAN CHRISTOPHER , LAWRENCE NICHOLAS
IPC分类号： G06F17/16 , G09G3/32
CPC分类号： G06F17/16 , G09G3/2022 , G09G3/2081 , G09G3/3216 , G09G3/3283 , G09G2310/0208 , G09G2320/0276
摘要： This invention generally relates to data processing hardware, and more particularly to hardware accelerators and related methods for matrix factorisation especially non- negat ive matrix factorisation (NMF). Embodiments of the invention are particularly useful for driving electroluminescent displays such as OLED displays. A matrix factorisation hardware accelerator for determining a pair of factor matrices (R;C) which when multiplied together approximate a target matrix, the hardware accelerator comprising: an input to receive an input data matrix representing said target matrix; a first factor matrix memory for storing row and column data for a first factor matrix (R), said first factor matrix memory having a plurality of first data buses each associated with a respective block of said first factor matrix memory for accessing first factor matrix column data stored in the block; a second factor matrix memory for storing row and column data for a second factor matrix (C), said second factor matrix memory having a plurality of second data buses each associated with a respective block of said second factor matrix memory for accessing second factor matrix row data stored in the block; a matrix of processor blocks, each processor block having: a first processor block data bus coupled to one of said first data buses, a second processor block data bus coupled to one of said second data buses, and a result data output; a processor memory block for storing a portion of a matrix (Q) representing a difference between a product of said pair of factor matrices and said target matrix; and a data processor comprising at least one multiply-add unit, said data processor having a first input coupled to said processor memory block and a second input coupled to one or both of said first and second processor block data buses and having an output coupled to said result data output; and control circuitry to control writing of data from said input into said processor memory blocks of said matrix of processor blocks, to control reading of data from said first and second factor matrix memories for provision to said matrix of processor blocks, and to control writing of data derived from said result data outputs back to said first and second factor matrix memories to perform said matrix factorisation.
摘要翻译：本发明一般涉及数据处理硬件，更具体地涉及用于矩阵分解的硬件加速器和相关方法，特别是非负矩阵因子分解（NMF）。本发明的实施例对于驱动诸如OLED显示器的电致发光显示器特别有用。一种用于确定一对因子矩阵（R; C）的矩阵分解硬件加速器，当一对乘以目标矩阵时，所述硬件加速器包括：用于接收表示所述目标矩阵的输入数据矩阵的输入; 用于存储用于第一因子矩阵（R）的行和列数据的第一因子矩阵存储器，所述第一因子矩阵存储器具有多个第一数据总线，每个第一数据总线与所述第一因子矩阵存储器的相应块相关联，用于访问第一因子矩阵列存储在块中的数据; 用于存储第二因子矩阵（C）的行和列数据的第二因子矩阵存储器，所述第二因子矩阵存储器具有多个第二数据总线，每个第二数据总线与所述第二因子矩阵存储器的相应块相关联，用于访问第二因子矩阵行存储在块中的数据; 处理器块的矩阵，每个处理器块具有：耦合到所述第一数据总线之一的第一处理器块数据总线，耦合到所述第二数据总线之一的第二处理器块数据总线和结果数据输出; 处理器存储块，用于存储表示所述一对因子矩阵和所述目标矩阵的乘积之间的差的矩阵（Q）的一部分; 以及包括至少一个乘法单元的数据处理器，所述数据处理器具有耦合到所述处理器存储器块的第一输入和耦合到所述第一和第二处理器块数据总线中的一个或两者的第二输入，并且具有耦合到表示结果数据输出; 以及控制电路，用于控制将数据从所述输入写入到所述处理器块矩阵的所述处理器存储器块中，以控制从所述第一和第二因子矩阵存储器读取数据以供给所述矩阵的处理器块，并且控制写入从所述结果数据导出的数据输出回所述第一和第二因子矩阵存储器以执行所述矩阵分解。

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