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1. 发明申请

WO0208966A3 METHOD AND SYSTEM FOR VERIFYING MODULES DESTINED FOR GENERATING CIRCUITS 审中-公开
标题翻译：用于生成电路的验证模块的方法和系统
公开(公告)号：WO0208966A3
公开(公告)日：2003-01-09
申请号：PCT/IT0100378
申请日：2001-07-17
申请人： TELECOM ITALIA LAB SPA , BOLLANO GIANMARIO , ETTORRE DONATO , TUROLLA MAURA , VALENTINI MARCELLO
发明人： BOLLANO GIANMARIO , ETTORRE DONATO , TUROLLA MAURA , VALENTINI MARCELLO
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Models destined for verification are described at the level of synthesizable description (for example VHDL). The synthesizable description (200) is automatically converted (300) into a C++ model (200'). This allows verification of the correctness of the synthesizable description by comparing the results of a verification carried out on the original description from the cell in C++ with the results of a similar verification of the C++ model obtained by automatic conversion of the synthesizable description. It is also possible to make the C++ model obtained by automatic conversion (200') to interact with a system model including blocks (201, 202, 203) of a system model at C++ level, in particular with the possibility of producing concurrent events that occur in correspondence with a main timing signal source.
摘要翻译：用于验证的模型在可综合描述的级别（例如VHDL）进行描述。可综合描述（200）被自动转换（300）为C ++模型（200'）。这允许通过将来自C ++中的单元的原始描述的验证结果与通过可合成描述的自动转换获得的C ++模型的类似验证的结果进行比较来验证可综合描述的正确性。也可以使通过自动转换（200'）获得的C ++模型与包括C ++级别的系统模型的块（201,202,203）的系统模型交互，特别是具有产生并发事件的可能性与主定时信号源对应地发生。

2. 发明申请

WO0233834A9 MODULE FOR GENERATING CIRCUITS FOR DECODING CONVOLUTIONAL CODES, RELATED METHOD AND CIRCUIT 审中-公开
标题翻译：用于解码卷积码的电路模块，相关方法和电路
公开(公告)号：WO0233834A9
公开(公告)日：2002-11-28
申请号：PCT/IT0100514
申请日：2001-10-11
申请人： TELECOM ITALIA LAB SPA , BOLLANO GIANMARIO , ETTORRE DONATO , TUROLLA MAURA
发明人： BOLLANO GIANMARIO , ETTORRE DONATO , TUROLLA MAURA
IPC分类号： G06F17/50 , H03M13/29 , H03M13/41
CPC分类号： H03M13/6516 , G06F17/5045 , H03M13/2957
摘要： The present invention relates to a module (50) for generating integrated decoding circuits for use, in particular, in turbo devices, to the method for defining the characteristics of and generating convolutional decoding circuits, and to the circuit that can be obtained with said module (50). The module (50) is parametric and, thanks to this feature, makes it possible to generate decoding circuits having different performance characteristics which are such that they can be used in turbo devices employing different decoding modes and different architectures. In addition, the module (50) makes it possible to generate decoding circuits whose distinguishing feature is that they can manage a plurality of generator polynomials selectively and can thus be used in asymmetrical turbo devices.
摘要翻译：本发明涉及用于产生集成解码电路的模块（50），特别是用于涡轮设备中，用于定义卷积解码电路的特性并产生卷积解码电路的方法以及可以用所述模块（50）。模块（50）是参数化的，并且由于该特征，使得可以生成具有不同性能特征的解码电路，使得它们可以用于采用不同解码模式和不同体系结构的涡轮设备中。另外，模块（50）能够生成解码电路，其区别特征是它们可以选择性地管理多个生成多项式，因此可以用于不对称的涡轮设备中。

3. 发明申请

WO03007194A2 METHOD FOR GENERATING ELECTRONIC CIRCUITS 审中-公开
标题翻译：电子电路生成方法
公开(公告)号：WO03007194A2
公开(公告)日：2003-01-23
申请号：PCT/IT0200449
申请日：2002-07-09
申请人： TELECOM ITALIA LAB SPA , BOLLANO GIANMARIO , TUROLLA MAURA , VALENTINI MARCELLO , VERCELLI STEFANO
发明人： BOLLANO GIANMARIO , TUROLLA MAURA , VALENTINI MARCELLO , VERCELLI STEFANO
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： The present invention relates to a method for obtaining electronic circuits wherein the design steps (100) constituted by a first development and testing cycle (200), of the functional type, and a second development and testing cycle (300), of the architectural type, are managed using, as inputs, for both cycles (200 and 300) the same configuration files (140) and stimuli (150) and generating, at the output, results having equivalent (230, 330) and comparable (333) formats. Thanks to these characteristics, it is possible to conduct in integrated fashion functional tests (220) and architectural tests (320) on corresponding functional and architectural models of electronic circuits and verify the perfect correspondence between the different types of models as the configurations files (140) and stimuli (150) vary.
摘要翻译：本发明涉及一种用于获得电子电路的方法，其中由建筑类型的功能类型的第一开发和测试周期（200）和第二开发和测试周期（300）构成的设计步骤（100）使用相同配置文件（140）和刺激（150）的两个周期（200和300）作为输入进行管理，并且在输出处生成具有等同（230,330）和可比较（333）格式的结果。由于这些特性，可以在电子电路的相应功能和架构模型上进行集成式功能测试（220）和架构测试（320），并验证不同类型型号之间的完美对应关系作为配置文件（140 ）和刺激（150）不同。

4. 发明申请

WO0210995A3 MODULE FOR GENERATING CIRCUITS FOR ANALYSING BIT STRINGS INSIDE DATA CELLS, METHOD FOR GENERATING THIS TYPE OF CIRCUIT AND RELATIVE CIRCUIT 审中-公开
标题翻译：产生电路分析数据单元内的位串，产生这种电路和相关电路的方法
公开(公告)号：WO0210995A3
公开(公告)日：2002-12-27
申请号：PCT/IT0100018
申请日：2001-01-16
申请人： TELECOM ITALIA LAB SPA , BOLLANO GIANMARIO , CLARETTO SERAFINO , TUROLLA MAURA
发明人： BOLLANO GIANMARIO , CLARETTO SERAFINO , TUROLLA MAURA
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045
摘要： This invention refers to a module (10) for generating integrated circuits suitable for analysing and validating bit strings inside telecommunications data cells, to the method for defining the structure and characteristics of such module and the integrated circuits that can be generated and to the integrated circuit that can be obtained with such module (10). The module (10), called parser, is parametric and makes it possible to generate parser circuits for many protocols because of such characteristic; the module (10), also, makes it possible, by means of a module REGFILE_2OUT (12), to generate programmable parser circuits and, by means of a module LOGIC_OPER (22) that can generate several analysis and validation devices, to execute in parallel bit string analysis inside telecommunications data cells.
摘要翻译：本发明涉及一种用于生成适合于分析和验证电信数据单元内的比特串的集成电路的模块（10），用于定义这种模块的结构和特性以及可生成的集成电路和集成电路可以用这种模块（10）获得。称为语法分析器的模块（10）是参数化的并且由于这种特性使得可以为许多协议生成语法分析器电路; 模块10还使得借助于模块REGFILE_2OUT（12）能够生成可编程分析器电路并且借助于可以生成若干分析和验证设备的模块LOGIC_OPER（22）来执行电信数据单元内的并行位串分析。

5. 发明申请

WO2006066604A8 METHOD AND SYSTEM FOR ACCESS CONTROL AND DATA PROTECTION IN DIGITAL MEMORIES, RELATED DIGITAL MEMORY AND COMPUTER PROGRAM PRODUCT THEREFOR 审中-公开
标题翻译：数字存储器中的访问控制和数据保护的方法和系统，相关的数字存储器和计算机程序产品
公开(公告)号：WO2006066604A8
公开(公告)日：2007-07-05
申请号：PCT/EP2004014611
申请日：2004-12-22
申请人： TELECOM ITALIA SPA , BIANCO ALBERTO , COLAZZO LAURA , RICCIATO FABIO , TUROLLA MAURA , VARRIALE ANTONIO
发明人： BIANCO ALBERTO , COLAZZO LAURA , RICCIATO FABIO , TUROLLA MAURA , VARRIALE ANTONIO
IPC分类号： G06F1/00
CPC分类号： G06Q20/3555 , G06F12/0223 , G06F12/1466 , G06F12/1491 , G06F21/78 , G06Q20/341 , G06Q20/35765 , G07F7/1008
摘要： A digital memory (50 to 70), such as a memory card for mobile communication equipment, is adapted to be accessed by a plurality of users and have protected data stored therein. The memory (50 to 70) is dynamically partitionable in private memory areas (68) for storing data therein and has associated a secrecy tool (58 to 62) for securely allocating to the users respective private memory areas (68) and permitting the users to access the respective private areas (68) via a secure session channel to perform read/write commands (20 to 28) in said respective private areas. Typically, the memory/card includes: a card interface controller (50) for managing a physical communication layer between the digital memory and external host equipment, an internal memory (68) having associated a hardware lock (66) to control access to the internal memory (68), a set of cryptographic modules (58, 60, 52) to manage the secure session channel between the users and said digital memory, and a memory certificate (70) for certifying a 25 public key associated with the digital memory.
摘要翻译：诸如用于移动通信设备的存储卡的数字存储器（50至70）适于被多个用户访问并且具有存储在其中的保护数据。存储器（50至70）可在专用存储器区域（68）中动态分区，用于在其中存储数据，并且具有与秘密工具（58至62）相关联的用于对用户安全分配各自的专用存储器区域（68）并允许用户经由安全会话信道访问相应的专用区域（68），以在所述各个私人区域中执行读/写命令（20至28）。通常，存储器/卡包括：卡接口控制器（50），用于管理数字存储器和外部主机设备之间的物理通信层;内部存储器（68），其具有关联硬件锁（66）以控制对内部存储器（68），用于管理用户和所述数字存储器之间的安全会话通道的一组加密模块（58,60,52）以及用于证明与数字存储器相关联的25个公共密钥的存储器证书（70）。

6. 发明申请

WO2008037286A3 USE, PROVISION, CUSTOMIZATION AND BILLING OF SERVICES FOR MOBILE USERS THROUGH DISTINCT ELECTRONIC APPARATUSES 审中-公开
标题翻译：移动电子设备的移动用户的使用，条款，定制和付费
公开(公告)号：WO2008037286A3
公开(公告)日：2008-12-11
申请号：PCT/EP2006009471
申请日：2006-09-29
申请人： TELECOM ITALIA SPA , VARRIALE ANTONIO , MANGIABENE SIMONETTA , ALESSIO ELISA , TUROLLA MAURA , MARCELLI MAURIZIO
发明人： VARRIALE ANTONIO , MANGIABENE SIMONETTA , ALESSIO ELISA , TUROLLA MAURA , MARCELLI MAURIZIO
IPC分类号： G06F21/34 , H04W4/00 , H04W8/26 , H04W12/06 , H04W88/02
CPC分类号： H04L63/0853 , G06F21/34 , G06F2221/2149 , H04W4/00 , H04W8/26 , H04W12/06 , H04W88/02
摘要： An office electronic apparatus is associated to an apparatus card and is able to use or provide a service by means of identification information; the identification information allows billing of the use or provision of the service. A mobile telephone terminal is associated to a subscriber card storing subscriber identification information. According to the method of the present invention, at least the subscriber identification information and preferably also subscriber authentication information are transferred from the mobile telephone terminal to an office electronic apparatus when the said mobile telephone terminal is in proximity of the office electronic apparatus, the transferred information is stored into the apparatus card of the office electronic apparatus, and the service is autonomously used or provided by the office electronic apparatus by means of the transferred information.
摘要翻译：办公室电子设备与设备卡相关联，并且能够通过识别信息使用或提供服务; 识别信息允许计费使用或提供服务。移动电话终端与存储用户识别信息的用户卡相关联。根据本发明的方法，当所述移动电话终端位于办公室电子设备附近时，至少用户识别信息，优选地还将用户认证信息从移动电话终端传送到办公室电子设备，信息被存储到办公室电子设备的设备卡中，并且该服务由办公室电子设备通过传送的信息自主使用或提供。

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