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1. 发明申请

WO2021177991A1 SEMICONDUCTOR DEVICE CONTAINING TUBULAR LINER SPACER FOR LATERAL CONFINEMENT OF SELF-ALIGNED SILICIDE PORTIONS AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：WO2021177991A1
公开(公告)日：2021-09-10
申请号：PCT/US2020/038455
申请日：2020-06-18
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka , KITA, Yosuke
IPC分类号： H01L21/768 , H01L29/78 , H01L21/285 , H01L29/66
摘要： A semiconductor structure includes a semiconductor channel of a first conductivity type located between a first and second active regions having a doping of a second conductivity type that is opposite of the first conductivity type, a gate stack structure that overlies the semiconductor channel, and includes a gate dielectric and a gate electrode, a first metal-semiconductor alloy portion embedded in the first active region, and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion, and contains a first tubular liner spacer including a first annular bottom surface, a first metallic nitride liner contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including bottom surface of the first tubular liner spacer, and a first metallic fill material portion embedded in the first metallic nitride liner.

2. 发明申请

WO2022260710A1 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED BIT LINE CONTACTS AND METHODS FOR FORMING THE SAME 审中-公开
公开(公告)号：WO2022260710A1
公开(公告)日：2022-12-15
申请号：PCT/US2022/011032
申请日：2022-01-03
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka , OSAWA, Yusuke , ISHIKAWA, Kensuke , MUSHIGA, Mitsuteru , KAWASAKI, Motoki , YADA, Shinsuke , MIYAMOTO, Masato , FUKATA, Syo , KASHIMURA, Takashi , FUJINO, Shigehiro
IPC分类号： H01L23/522 , H01L21/768
摘要： A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

3. 发明申请

WO2018156222A1 SEMICONDUCTOR DEVICE CONTAINING MULTILAYER TITANIUM NITRIDE DIFFUSION BARRIER AND METHOD OF MAKING THEREOF 审中-公开
公开(公告)号：WO2018156222A1
公开(公告)日：2018-08-30
申请号：PCT/US2017/062204
申请日：2017-11-17
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka , ISHIKAWA, Kensuke , INOUE, Shinya , SANO, Michiaki
IPC分类号： H01L21/285 , H01L21/768 , H01L29/45 , H01L29/66
摘要： A semiconductor device includes a silicon surface (1402), a titanium silicide layer (1404) contacting the silicon surface, a first titanium nitride layer (1406) located over the titanium silicide layer, a titanium oxynitride layer (1512) contacting the first titanium nitride layer, a second titanium nitride layer (1516) contacting the titanium oxynitride layer, and a metal fill layer (84B) located over the second titanium nitride layer.

4. 发明申请

WO2023018452A1 THREE-DIMENSIONAL MEMORY DEVICE INCLUDING ALUMINUM ALLOY WORD LINES AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：WO2023018452A1
公开(公告)日：2023-02-16
申请号：PCT/US2022/027545
申请日：2022-05-04
申请人： SANDISK TECHNOLOGIES LLC
发明人： CHEN, Linghan , MAKALA, Raghuveer S. , AMANO, Fumitaka
IPC分类号： H01L27/11551 , H01L29/80 , H01L29/49 , H01L21/02
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

5. 发明申请

WO2018004804A1 THREE DIMENSIONAL MEMORY DEVICE CONTAINING MULTILAYER WORDLINE BARRIER FILMS AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：含有多层字线阻挡膜的三维存储器装置及其制造方法
公开(公告)号：WO2018004804A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/029363
申请日：2017-04-25
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARANGPANI, Rahul , MAKALA, Raghuveer S. , SHUKLA, Keerti , ZHOU, Fei , PERI, Somesh , AMANO, Fumitaka
IPC分类号： H01L21/28 , H01L29/792 , H01L27/11582
CPC分类号： H01L27/11556 , H01L21/76847 , H01L23/53266 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/40117 , H01L29/7926
摘要： Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
摘要翻译：通过交替堆叠的绝缘层和牺牲材料层形成存储器堆叠结构。通过去除对绝缘层和存储器堆叠结构有选择性的牺牲材料层来形成后侧凹槽。在形成金属填充材料层之前，在后侧凹槽中形成包括晶体导电阻挡层和非晶态阻挡层的阻挡层叠层。

6. 发明申请

WO2023075856A2 HIGH ASPECT RATIO VIA FILL PROCESS EMPLOYING SELECTIVE METAL DEPOSITION AND STRUCTURES FORMED BY THE SAME 审中-公开
公开(公告)号：WO2023075856A2
公开(公告)日：2023-05-04
申请号：PCT/US2022/029316
申请日：2022-05-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARANGPANI, Rahul , MAKALA, Raghuveer S. , AMANO, Fumitaka , ISHIKAWA, Kensuke
IPC分类号： H10B43/50 , H10B41/50 , H10B43/27 , H10B41/27 , H01L21/768
摘要： A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

7. 发明申请

WO2018208356A1 MULTI-LAYER BARRIER FOR CMOS UNDER ARRAY TYPE MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开
公开(公告)号：WO2018208356A1
公开(公告)日：2018-11-15
申请号：PCT/US2018/019177
申请日：2018-02-22
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka
IPC分类号： H01L29/45 , H01L21/768 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11582
CPC分类号： H01L27/11582 , H01L21/26513 , H01L21/76846 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L23/485 , H01L23/53209 , H01L23/53238 , H01L23/53266 , H01L27/11521 , H01L27/11526 , H01L27/11556 , H01L27/11568 , H01L27/11573 , H01L29/167 , H01L29/456
摘要： A semiconductor structure includes a doped semiconductor material portion, a metal- semiconductor alloy portion contacting the doped semiconductor material portion, a device contact via structure in direct contact with the metal-semiconductor alloy portion, and at least one dielectric material layer laterally surrounding the device contact via structure. The device contact via structure includes a barrier stack and a conductive fill material portion. The barrier stack includes at least two metal nitride layers and at least one nitrogen- containing material layer containing nitrogen and an element selected from silicon or boron.

8. 发明申请

WO2018080634A1 THREE-DIMENSIONAL MEMORY DEVICE HAVING NON-UNIFORM SPACING AMONG MEMORY STACK STRUCTURES AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：存储器堆栈结构中具有非均匀间隔的三维存储器器件及其制造方法
公开(公告)号：WO2018080634A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/049674
申请日：2017-08-31
申请人： SANDISK TECHNOLOGIES LLC
发明人： MIZUTANI, Yuki , OGAWA, Hiroyuki , TOYAMA, Fumiaki , HIGASHITANI, Masaaki , AMANO, Fumitaka , FUNAYAMA, Kota , UEDA, Akihiro
IPC分类号： H01L27/11565 , H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/0692 , H01L29/78642 , H01L29/7926
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.
摘要翻译：在衬底上形成交替堆叠的绝缘层和牺牲材料层。包括存储器膜和垂直半导体沟道的存储器堆叠结构通过交替堆叠以阵列配置形成。通过交替堆叠形成沿纵向方向延伸的背侧沟槽。通过去除牺牲材料层形成背侧凹陷。通过以不均匀间距布置存储器堆叠结构，可以在没有空隙或具有最小空隙的情况下执行用导电层填充背侧凹槽。非均匀间距可以沿垂直于纵向方向的方向，使得存储器堆叠结构之间的最近邻近距离在背侧沟槽之间最小。可选地或另外地，可以沿纵向方向调节节距以提供垂直于纵向方向延伸的更宽的间隔区域。

9. 发明申请

WO2018017182A3 THREE-DIMENSIONAL MEMORY DEVICE HAVING MULTI-LAYER DIFFUSION BARRIER STACK FOR METAL CONTROL GATE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有用于金属控制栅极的多层扩散阻挡堆叠的三维存储器装置及其制造方法
公开(公告)号：WO2018017182A3
公开(公告)日：2018-01-25
申请号：PCT/US2017/032738
申请日：2017-05-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka
IPC分类号： H01L21/28 , H01L27/11582
摘要： An alternating stack of insulating layers (32) and spacer material layers is formed over a substrate. Memory stack structures (55) are formed through the alternating stack. The spacer material layers are removed to form backside recesses. The backside recesses are sequentially filled with a continuous layer stack including a first continuous metallic nitride layer (462), a continuous tungsten layer (464), a second continuous metallic nitride layer (466), and a continuous metal fill layer (468). The continuous layer stack is patterned to form electrically conductive layers. Each electrically conductive layer includes a liner stack (46) of the first metallic nitride liner, the tungsten liner, and the second metallic nitride liner. The liner stack is a diffusion barrier for high diffusivity species such as fluorine and boron.
摘要翻译：在衬底上形成交替堆叠的绝缘层（32）和间隔材料层。存储器堆叠结构（55）通过交替堆叠形成。间隔物材料层被去除以形成背侧凹部。后侧凹槽顺序地填充有包括第一连续金属氮化物层（462），连续钨层（464），第二连续金属氮化物层（466）和连续金属填充层（468）的连续层堆叠。连续层堆叠被图案化以形成导电层。每个导电层包括第一金属氮化物衬垫，钨衬垫和第二金属氮化物衬垫的衬垫叠层（46）。衬垫叠层是高扩散率物质如氟和硼的扩散阻挡层。

10. 发明申请

WO2018017182A2 THREE-DIMENSIONAL MEMORY DEVICE HAVING MULTI-LAYER DIFFUSION BARRIER STACK AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有多层扩散屏障堆叠的三维存储器装置及其制造方法
公开(公告)号：WO2018017182A2
公开(公告)日：2018-01-25
申请号：PCT/US2017/032738
申请日：2017-05-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： AMANO, Fumitaka
IPC分类号： H01L21/28 , H01L27/11582
CPC分类号： H01L27/11582 , H01L28/00 , H01L29/40117
摘要： An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are removed to form backside recesses. The backside recesses are sequentially filled with a continuous layer stack including a first continuous metallic nitride layer, a continuous tungsten layer, a second continuous metallic nitride layer, and a continuous metal fill layer. The continuous layer stack is patterned to form electrically conductive layers. Each electrically conductive layer includes a liner stack of a first metallic nitride liner, a tungsten liner, and a second metallic nitride liner. The liner stack is a diffusion barrier for high diffusivity species such as fluorine and boron.
摘要翻译：在衬底上形成交替堆叠的绝缘层和间隔材料层。存储器堆栈结构通过交替堆栈形成。间隔物材料层被去除以形成背侧凹部。背面凹部依次填充有包括第一连续金属氮化物层，连续钨层，第二连续金属氮化物层和连续金属填充层的连续层堆叠。连续层堆叠被图案化以形成导电层。每个导电层包括第一金属氮化物衬垫，钨衬垫和第二金属氮化物衬垫的衬垫叠层。衬垫叠层是高扩散率物质如氟和硼的扩散阻挡层。

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