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1. 发明申请

WO2016064512A1 METHODS FOR REDUCING BODY EFFECT AND INCREASING JUNCTION BREAKDOWN VOLTAGE 审中-公开
标题翻译：降低机体效应并增加断点电压的方法
公开(公告)号：WO2016064512A1
公开(公告)日：2016-04-28
申请号：PCT/US2015/051283
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： HSIUNG, Chia-Lin , TOYAMA, Fumiaki , HIGASHITANI, Masaaki
IPC分类号： G11C16/08 , H01L27/115
CPC分类号： G11C16/10 , G11C8/08 , G11C16/08 , G11C16/12 , H01L27/0207 , H01L27/11529
摘要： Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect.
摘要翻译：描述了用于减小由于体效应引起的晶体管阈值电压增加并增加晶体管结的结击穿电压的方法。晶体管可以包括在编程操作期间将编程电压（例如，24V）传送到存储器阵列的字线的NMOS晶体管。在一些情况下，第一多晶硅屏蔽可以位于晶体管的栅极的第一距离内，并且可以包括与晶体管的栅极直接相邻的第一多晶硅结构。第一多晶硅屏蔽可以沿第一方向（例如，在晶体管的沟道长度方向）上布置。在编程操作期间，第一多晶屏蔽可被偏压到大于接地（例如10V）的第一电压，以减少由于身体效应引起的晶体管的阈值电压的增加。

2. 发明申请

WO2014158739A1 COMPENSATION FOR TEMPERATURE-DEPENDENCE OF BIT LINE RESISTANCE 审中-公开
标题翻译：补偿温度依赖于线路电阻
公开(公告)号：WO2014158739A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/019738
申请日：2014-03-01
申请人： SANDISK TECHNOLOGIES INC.
发明人： HSIUNG, Chia-Lin , DUNGA, Mohan , MUI, Man L , HIGASHITANI, Masaaki
IPC分类号： G11C11/56 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C7/04 , G11C7/12 , G11C11/5642 , G11C16/0483 , G11C16/24
摘要： Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage.
摘要翻译：用于通过补偿位线或其他控制线的电阻中的基于温度的变化的变化来读取和验证操作期间感测存储器单元的阈值电压的技术。正在感测的存储单元位于存储器阵列中的块中，并且块位于一组块中。位线的一部分在块组和感测分量之间延伸，并且具有基于长度/距离和温度的电阻。各种参数可以随着温度和块组而改变，以提供补偿，包括位线电压，所选字线电压，源极线电压，感测时间和/或感测电流或电压。

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