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1. 发明申请

WO2006065501A1 MEMORY SENSING CIRCUIT AND METHOD FOR LOW VOLTAGE OPERATION 审中-公开
标题翻译：存储感测电路和低电压运行方法
公开(公告)号：WO2006065501A1
公开(公告)日：2006-06-22
申请号：PCT/US2005/042854
申请日：2005-11-28
申请人： SANDISK CORPORATION , CERNEA, Raul-adrian
发明人： CERNEA, Raul-adrian
IPC分类号： G11C7/06 , G11C16/26 , G11C11/56
CPC分类号： G11C11/5642 , G11C7/062 , G11C7/067 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/28 , G11C2207/063 , G11C2211/5621 , G11C2216/14 , G11C2216/22
摘要： A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop thereacross in a predetermined period is used to indicate the magnitude of the conduction current. The voltage cannot drop below a minimum level imposed by a circuit for maintaining the constant voltage condition on the bit line. A voltage shifter is used to boost the voltage during the discharge and to unboost the voltage after the discharge, so that the change in voltage drop properly reflects the rate of discharge without running into the minimum level.
摘要翻译：感测模块通过在恒定电压条件下经由耦合位线检测存储器单元的传导电流的读出放大器工作，以使位线到位线耦合最小化。通过在预定时间段内的电压降的变化来测量专用电容器的放电率，用于表示导通电流的大小。电压不能下降到电路所施加的最小电平以保持位线上的恒定电压状态。电压移位器用于在放电期间升高电压并且在放电之后解除电压，使得电压降的变化适当地反映放电速率而不会达到最小水平。

2. 发明申请

WO2007001911A1 COMPENSATION CURRENTS IN NON-VOLATILE MEMORY READ OPERATIONS 审中-公开
标题翻译：非易失性存储器读取操作中的补偿电流
公开(公告)号：WO2007001911A1
公开(公告)日：2007-01-04
申请号：PCT/US2006/023541
申请日：2006-06-15
申请人： SANDISK CORPORATION , CERNEA, Raul-adrian
发明人： CERNEA, Raul-adrian
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C7/02 , G11C7/12 , G11C16/26
摘要： Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.
摘要翻译：存储在非易失性存储单元的浮动栅极上的视在电荷的变化可能由于基于存储在相邻浮动栅极中的电荷的电场的耦合而发生。表观电荷的偏移可能导致误差读数，因为提高了视在阈值电压，从而降低了感测的存储单元的传导电流。所选择的存储器单元的读取处理考虑了一个或多个相邻存储器单元的状态。如果相邻存储器单元处于预定的一组编程状态中的一个或多个，则可以提供补偿电流以增加所选存储单元的表观传导电流。将初始化电压提供给编程的相邻存储器单元的位线，以在编程的相邻存储单元的位线和所选存储单元的位线之间产生补偿电流。

3. 发明申请

WO2007076414A2 REFERENCE SENSE AMPLIFIER AND METHOD FOR COMPENSATED SENSING IN NON-VOLATILE MEMORY 审中-公开
标题翻译：参考灵敏放大器和用于非易失性存储器中的补偿感测的方法
公开(公告)号：WO2007076414A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062429
申请日：2006-12-20
申请人： SANDISK CORPORATION , CHAN, Siu Lung , CERNEA, Raul-adrian
发明人： CHAN, Siu Lung , CERNEA, Raul-adrian
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/14 , G11C16/26 , G11C16/32 , G11C2207/063
摘要： One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
摘要翻译：用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有类似特性和操作条件的参考感测放大器定时的信号控制。在一个方面中，感测周期由感测参考电流的参考感测放大器何时检测到预期状态来确定。另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。当这些确定的时序用于控制一个或多个读出放大器时，跟踪环境和系统变化。

4. 发明申请

WO2010025058A1 NON-VOLATILE MEMORY AND METHOD FOR RAMP-DOWN PROGRAMMING 审中-公开
标题翻译：非易失性存储器和减速编程方法
公开(公告)号：WO2010025058A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/054215
申请日：2009-08-18
申请人： SANDISK CORPORATION , CERNEA, Raul-adrian
发明人： CERNEA, Raul-adrian
IPC分类号： G11C16/10 , G11C16/12 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/12 , G11C2211/5621
摘要： A ramp-down programming voltage is used to program a group of nonvolatile memory cells in parallel, step by step from a highest step to a lowest step. Overall programming time is improved when a conventional setup for program inhibit together with a verify after each program step are avoided. A program voltage estimate is provided for each cell indicating the programming voltage expected to program the cell to its target. Initially, all but those cells having estimates at or above the current program voltage step will be program-inhibited. Thereafter, with each descending program voltage step, additional cells will be un-inhibited. Once un-inhibited, a cell need not be re-inhibited even if programmed to its target. This is because subsequent program steps are at lower voltages and ineffective in programming the cell beyond its target. The un-inhibit operation in one implementation amounts to simply pulling the associated bit lines to ground.
摘要翻译：使用斜坡编程电压来并行地编程一组非易失性存储器单元，从最高级到最低级逐步地编程。当避免在每个程序步骤之后的程序禁止的常规设置以及验证时，整体编程时间得到改善。为每个单元提供了一个程序电压估计，指示预期将该单元编程到其目标的编程电压。最初，除了那些具有或高于当前编程电压阶跃的估计的单元格将被程序禁止。此后，通过每个降序编程电压步骤，附加单元将被禁止。一旦未被禁止，即使编程到其目标，单元不需要被重新禁止。这是因为后续的程序步骤处于较低的电压，并且将单元编程超出其目标无效。在一个实现中的非禁止操作相当简单地将相关联的位线拉到地。

5. 发明申请

WO2008083136A2 RESISTANCE SENSING AND COMPENSATION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非易失性存储器的电阻检测和补偿
公开(公告)号：WO2008083136A2
公开(公告)日：2008-07-10
申请号：PCT/US2007/088786
申请日：2007-12-24
申请人： SANDISK CORPORATION , MOKHLESI, Nima , CERNEA, Raul-adrian
发明人： MOKHLESI, Nima , CERNEA, Raul-adrian
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/26
摘要： When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.
摘要翻译：当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。根据测量的电阻信息设置一个或多个读取参数。然后使用一个或多个参数执行读取过程。

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