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    • 2. 发明申请
    • SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL)
    • 用于数字相位锁定(DPLL)的时间到数字转换器(TDC)的校准功率增益窗口的系统和方法
    • WO2009132147A1
    • 2009-10-29
    • PCT/US2009/041461
    • 2009-04-22
    • QUALCOMM INCORPORATEDSUN, BoYANG, ZixiangSAHOTA, Gurkanwal, Singh
    • SUN, BoYANG, ZixiangSAHOTA, Gurkanwal, Singh
    • H03L7/085
    • H03L7/085H03L7/18H03L2207/50
    • A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
    • 公开了一种系统和方法,用于校准数字锁相环(DPLL)的时间 - 数字转换器(TDC)的上电门控窗口。 门控窗口被校准,以确保DPLL的正常运行,同时以高效的方式操作TDC。 特别地,该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号,将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。
    • 3. 发明申请
    • HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER
    • 高分辨率时间到数字转换器
    • WO2009111496A1
    • 2009-09-11
    • PCT/US2009/035913
    • 2009-03-03
    • QUALCOMM INCORPORATEDSUN, BoYANG, Zixiang
    • SUN, BoYANG, Zixiang
    • H03M1/20H03M1/50
    • G04F10/005
    • A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.
    • 时间 - 数字转换器(TDC)可以具有比逆变器的传播延迟更精细的分辨率。 在一个示例中,分数延迟元件电路接收TDC输入信号并由此产生作为第一信号的时移传真的第二信号。 第一信号被提供给第一延迟线时间戳电路(DLTC),第二信号被提供给第二DLTC。 第一DLTC产生指示参考输入信号与TDC的边缘和第一信号的边缘之间的时间的第一时间戳。 第二DLTC产生指示参考输入信号的边缘与第二信号的边缘之间的时间的第二时间戳。 组合第一和第二时间戳并且一起构成具有比第一或第二时间戳更精细的分辨率的高分辨率整体TDC时间戳。
    • 6. 发明申请
    • DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER
    • 数字锁相环与定位的时间到数字转换器
    • WO2009088790A1
    • 2009-07-16
    • PCT/US2008/088263
    • 2008-12-24
    • QUALCOMM IncorporatedSUN, BoSAHOTA, Gurkanwal SinghYANG, Zixiang
    • SUN, BoSAHOTA, Gurkanwal SinghYANG, Zixiang
    • H03L7/08H03L7/087
    • H03L7/0802H03L7/087
    • A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
    • 数字PLL(DPLL)包括时间 - 数字转换器(TDC)和控制单元。 定期启用TDC以持续短时间量化相位信息,并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号,并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。 控制单元基于主参考信号生成使能信号,并使能和禁止具有使能信号的TDC。 在一种设计中,控制单元延迟主参考信号以获得第一参考信号和第二参考信号,基于主参考信号和第二参考信号产生使能信号,并且将主时钟信号与使能信号 以获得TDC的第一个时钟信号。
    • 7. 发明申请
    • SYSTEM AND METHOD FOR BIASING ACTIVE DEVICES
    • 用于偏置活动设备的系统和方法
    • WO2011072248A1
    • 2011-06-16
    • PCT/US2010/059936
    • 2010-12-10
    • QUALCOMM INCORPORATEDSUN, Bo
    • SUN, Bo
    • G05F1/46H03M1/80H03G3/30
    • G05F1/46H03F1/0261H03F1/223H03F3/195H03F2200/108H03F2200/27H03F2200/294H03F2200/321H04B2001/6908
    • An apparatus for generating a bias voltage for an active device is disclosed, comprising a first voltage source, a capacitive element adapted to generate a charge in response to the first voltage source, and a first switching element adapted to deliver the charge to generate the bias voltage for the active device. The apparatus may comprise a controller adapted to control a capacitive element based on one or more characteristics of the active device. Alternatively, the controller may also control the capacitance of the capacitive element based on a reference voltage that is, in turn, based on one or more characteristics of the active device. The apparatus may also comprise a second voltage source adapted to generate a second voltage from which the bias voltage may be generated. The second voltage may be based on one or more characteristics of the active device. The apparatus may comprise a second switching element adapted to selectively enable and disable the active device.
    • 公开了一种用于产生用于有源器件的偏置电压的装置,包括:第一电压源,适于响应于第一电压源产生电荷的电容元件;以及适于传送电荷以产生偏置的第一开关元件 有源器件的电压。 该装置可以包括适于基于有源装置的一个或多个特性来控制电容元件的控制器。 或者,控制器还可以基于参考电压来控制电容元件的电容,参考电压又是基于有源器件的一个或多个特性。 该装置还可以包括适于产生可产生偏置电压的第二电压的第二电压源。 第二电压可以基于有源器件的一个或多个特性。 该装置可以包括适于选择性地启用和禁用有源装置的第二开关元件。