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1. 发明申请

WO2012149569A1 SELF-BODY BIASING SENSING CIRCUIT FOR RESISTANCE-BASED MEMORIES 审中-公开
标题翻译：用于基于电阻的存储器的自身偏心感测电路
公开(公告)号：WO2012149569A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/035882
申请日：2012-04-30
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , JUNG, Youngdon , KIM, Jung Pill , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , JUNG, Youngdon , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C11/16 , G11C7/14 , G11C7/06 , G11C16/28 , G11C16/26 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit (302) has reference current transistors (310, 312) feeding a reference node (204) and a read current transistor (308) feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译：基于电阻的存储器感测电路（302）具有馈送参考节点（204）的参考电流晶体管（310,312）和馈送感测节点的读取电流晶体管（308），每个晶体管具有在正常衬底电压下的衬底主体待机模式并且在感测模式期间偏置在比正常衬底电压低的体偏置电压。在一个选项中，体偏置电压由参考节点上的参考电压确定。处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。

2. 发明申请

WO2011136965A1 INVALID WRITE PREVENTION FOR STT-MRAM ARRAY 审中-公开
标题翻译： STT-MRAM阵列的无效写防
公开(公告)号：WO2011136965A1
公开(公告)日：2011-11-03
申请号：PCT/US2011/032900
申请日：2011-04-18
申请人： QUALCOMM INCORPORATED , RYU, Kyungho , KIM, Jisu , JUNG, Seong-Ook , KANG, Seung H.
发明人： RYU, Kyungho , KIM, Jisu , JUNG, Seong-Ook , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659 , H01L43/12 , Y10T29/4902
摘要： In a Spin Transfer Torque Magnetoresi stive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. Write disturb is prevented by setting a voltage associated with unselected ones of the bit lines equal to a selected source line.
摘要翻译：在转移转矩磁阻随机存取存储器（STT-MRAM）中，位单元阵列可以具有基本上平行于字线的源极线。源极线可以基本上垂直于位线。源极线控制单元包括公共源极线驱动器和被配置为选择各个源极线的源极线选择器。源极线驱动器和源极线选择器可以以多路复用关系耦合。位线控制单元包括公共位线驱动器和多路复用关系的位线选择器。位线控制单元包括耦合在公共源线驱动器和位线选择线和位线之间的正沟道金属氧化物半导体（PMOS）元件。通过设置与未选择的位线等于所选择的源极线的电压来防止写入干扰。

3. 发明申请

WO2011091217A2 SYSTEM AND METHOD OF ADJUSTING A RESISTANCE-BASED MEMORY CIRCUIT PARAMETER 审中-公开
标题翻译：调整基于电阻的存储器电路参数的系统和方法
公开(公告)号：WO2011091217A2
公开(公告)日：2011-07-28
申请号：PCT/US2011/021988
申请日：2011-01-21
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H.
IPC分类号： G06F17/50 , G11C11/16 , G11C7/06
CPC分类号： G06F17/5036 , G06F2217/10 , G11C7/02 , G11C7/06 , G11C11/1673

4. 发明申请

WO2010002637A1 CONTROLLED VALUE REFERENCE SIGNAL OF RESISTANCE BASED MEMORY CIRCUIT 审中-公开
标题翻译：基于电阻的记忆电路的控制参考信号
公开(公告)号：WO2010002637A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/048301
申请日：2009-06-23
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung, H. , YOON, Sei, Seung
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung, H. , YOON, Sei, Seung
IPC分类号： G11C11/16
CPC分类号： G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.
摘要翻译：公开了基于电阻的存储器电路的受控值参考信号的系统和方法。在特定实施例中，公开了一种电路装置，其包括被配置为接收参考控制信号的第一输入。电路装置还包括响应于第一输入的输出，以选择性地向耦合到基于电阻的存储器单元的读出放大器提供受控值参考电压。

5. 发明申请

WO2011091207A1 RESISTANCE-BASED MEMORY WITH REDUCED VOLTAGE INPUT/OUTPUT DEVICE 审中-公开
标题翻译：具有降低电压输入/输出装置的基于电阻的存储器
公开(公告)号：WO2011091207A1
公开(公告)日：2011-07-28
申请号：PCT/US2011/021974
申请日：2011-01-21
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , KANG, Seung, H.
发明人： JUNG, Seong-Ook , KIM, Jisu , KANG, Seung, H.
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1673
摘要： A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit.
摘要翻译：公开了一种具有降压I / O装置的基于电阻的存储器。在特定实施例中，电路包括包括第一电阻存储器单元和第一负载晶体管的数据路径。参考路径包括第二电阻存储器单元和第二负载晶体管。第一负载晶体管和第二负载晶体管是适于在类似于电路内的核心晶体管的核心电源电压的负载电源电压下工作的输入和输出（I / O）晶体管。

6. 发明申请

WO2013003833A1 SENSING CIRCUIT 审中-公开
标题翻译：感应电路
公开(公告)号：WO2013003833A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/045173
申请日：2012-07-01
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , KIM, Jisu , RYU, Kyungho , KIM, Jung Pill , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , RYU, Kyungho , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C7/06 , G11C7/12 , G11C11/16 , G11C11/26 , G11C11/4091
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal - oxide - semiconductor (PMOS) transistor (102), a load PMOS transistor (104), and a clamp transistor (110) configured to clamp a voltage applied to a resistance based memory element (112) during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not- AND (NAND) circuit (106).
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管（102），负载PMOS晶体管（104）和钳位晶体管（110），其被配置为钳位施加到基于电阻的存储元件（112）的电压）。负载PMOS晶体管的栅极由非AND（NAND）电路（106）的输出控制。

7. 发明申请

WO2013003832A1 SENSING CIRCUIT 审中-公开
标题翻译：感应电路
公开(公告)号：WO2013003832A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/045172
申请日：2012-07-01
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , KIM, Jisu , RYU, Kyungho , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , RYU, Kyungho , KANG, Seung H.
IPC分类号： G11C7/06 , G11C7/12 , G11C11/16 , G11C16/26 , G11C11/4091
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1655 , G11C11/1673 , G11C11/4091 , G11C13/004 , G11C16/26 , G11C2207/002
摘要： A circuit (101) includes a degeneration p-channel metal - oxide - semiconductor (PMOS) transistor (102), a load PMOS transistor (104), and a clamp transistor (110) configured to clamp a voltage applied to a resistance based memory element (112) during a sensing operation. A gate of the load PMOS transistor (118) is controlled by an output (120) of an operational amplifier (106).
摘要翻译：电路（101）包括退化的p沟道金属氧化物半导体（PMOS）晶体管（102），负载PMOS晶体管（104）和钳位晶体管（110），其被配置为钳位施加到基于电阻的存储器元件（112）。负载PMOS晶体管（118）的栅极由运算放大器（106）的输出（120）控制。

8. 发明申请

WO2010148248A1 DIFFERENTIAL SENSE AMPLIFIER WITH CURRENT MIRRORING AND REFERENCE MEMORY CELL 审中-公开
标题翻译：具有电流反射和参考存储单元的差分感测放大器
公开(公告)号：WO2010148248A1
公开(公告)日：2010-12-23
申请号：PCT/US2010/039075
申请日：2010-06-17
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KIM, Jisu , KANG, Seung H.
发明人： JUNG, Seong-Ook , KIM, Jisu , KANG, Seung H.
IPC分类号： G11C7/06 , G11C11/16
CPC分类号： G11C7/062 , G11C11/1673
摘要： A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including a second load transistor. The second path is coupled to a third split path including a third load transistor and to a fourth split path including a fourth load transistor.
摘要翻译：公开了一种感测电路。感测电路包括第一路径，其包括第一电阻性存储器件和包括参考电阻存储器件的第二路径。第一路径被耦合到包括第一负载晶体管和包括第二负载晶体管的第二分路的第一分路。第二路径被耦合到包括第三负载晶体管的第三分路，以及包括第四负载晶体管的第四分路。

9. 发明申请

WO2012015754A3 LATCHING CIRCUIT 审中-公开
公开(公告)号：WO2012015754A3
公开(公告)日：2012-02-02
申请号：PCT/US2011/045222
申请日：2011-07-25
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , RYU, Kyungho , KIM, Jisu , KIM, Jung Pill , KANG, Seung H.
发明人： JUNG, Seong-Ook , RYU, Kyungho , KIM, Jisu , KIM, Jung Pill , KANG, Seung H.
IPC分类号： G11C7/06 , G11C7/20 , G11C11/16 , G11C14/00
摘要： A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.

10. 发明申请

WO2010080629A1 BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT 审中-公开
标题翻译：平衡基于电阻的信号电路的信号
公开(公告)号：WO2010080629A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/068799
申请日：2009-12-18
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
发明人： JUNG, Seong-Ook , KIM, Jisu , SONG, Jee-Hwan , KANG, Seung H. , YOON, Sei Seung , SANI, Mehdi Hamidi
IPC分类号： G11C11/16 , G11C7/06
CPC分类号： G11C7/14 , G11C7/12 , G11C11/1673
摘要： A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.
摘要翻译：公开了一种基于电阻的存储器电路。电路包括数据单元的第一晶体管负载和适于检测第一逻辑状态的位线。位线耦合到第一晶体管负载并耦合到具有磁隧道结（MTJ）结构的数据单元。当位线具有第一电压值时，位线适于检测具有逻辑1值的数据，并且当位线具有第二电压值时，检测具有逻辑零值的数据。电路还包括参考单元的第二晶体管负载。第二晶体管负载耦合到第一晶体管负载，并且第二晶体管负载具有相关联的参考电压值。诸如晶体管宽度的第一晶体管负载的特性是可调节的，以修改第一电压值和第二电压值，而基本上不改变参考电压值。

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