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1. 发明申请

WO2013082625A1 METHOD AND APPARATUS FOR SAVING PROCESSOR INFORMATION PRIOR TO A RESET FOR POST RESET EVALUATION 审中-公开
标题翻译：用于在复位后重新进行评估的方法和装置用于保存处理器信息
公开(公告)号：WO2013082625A1
公开(公告)日：2013-06-06
申请号：PCT/US2012/067652
申请日：2012-12-03
申请人： QUALCOMM INCORPORATED
发明人： SARTORIUS, Thomas Andrew , SINGH, Subodh
IPC分类号： G06F11/14
CPC分类号： G06F11/1441
摘要： A processor reset control circuit is configured to automatically capture a prereset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.
摘要翻译：处理器复位控制电路被配置为自动地捕获存储在一个或多个硬件寄存器中的处理器信息的预先存储值，作为复位操作状态机的一部分，并且在将处理器信息改变为其架构上所需的后置复位值之前。这种预复位处理器信息包括例如处理器程序计数器（PC）的一个或多个预复位值和操作状态模式寄存器的一个或多个预复位值，它们都可以被捕获在一个或多个更多的预复位捕获存储设备，然后可用于评估目的。这种预复位捕获存储设备响应于重置来存储预复位信息，并保持所存储的预复位信息直到发生另一个复位。

2. 发明申请

WO2017160464A1 SYSTEMS AND METHODS FOR IMPROVED DETECTION OF PROCESSOR HANG AND IMPROVED RECOVERY FROM PROCESSOR HANG IN A COMPUTING DEVICE 审中-公开
标题翻译：用于改善检测处理器吊挂和改善从计算装置中的处理器吊带回收的系统和方法
公开(公告)号：WO2017160464A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/018229
申请日：2017-02-16
申请人： QUALCOMM INCORPORATED
发明人： IDAPALAPATI, Anantha , PATIL, Ajaykumar Shankargouda , SINGH, Subodh , SOMANI, Ramswaroop , NEDANURI, Gopi Krishna , CHHABRA, Pawan , BANERJEE, Sarbartha , WONG, Victor
IPC分类号： G06F11/07
CPC分类号： G06F11/0757 , G06F11/0721 , G06F11/1441 , G06F13/24 , G06F13/28
摘要： Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.
摘要翻译：公开了用于改进的处理器挂起检测的系统和方法。示例性方法包括为片上系统（SoC）的多个处理器中的每一个设置具有挂起阈值的定时器。挂起阈值表示以微秒为单位的时间。所述方法进一步包括接收来自所述多个处理器中的每一个的第一心跳信号，其中所述检测逻辑硬件是耦合到所述多个处理器并且连接到所述定时器的挂起控制器。如果在定时器到期之前从多个处理器中的对应的一个处理器接收到第二心跳信号，则针对多个处理器中的每一个处理器重置定时器。或者，如果在定时器到期之前没有从多个处理器中的相应处理器接收到第二心跳信号，则生成挂起事件通知。

3. 发明申请

WO2017105886A1 DYNAMIC PREDICTIVE WAKE-UP TECHNIQUES 审中-公开
标题翻译：动态预测唤醒技术
公开(公告)号：WO2017105886A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/064893
申请日：2016-12-05
申请人： QUALCOMM INCORPORATED
发明人： NAMPOOTHIRI, Sankaran , AGARAM, Narasimhan, Venkata , GERBER, Nir , SINGH, Subodh
IPC分类号： G06F1/32
CPC分类号： G06F9/4418 , G06F1/3206 , G06F1/3287 , G06F3/061 , G06F3/0659 , G06F3/0673 , G06F13/24
摘要： Dynamic predictive wake-up techniques are disclosed. A central processing unit (CPU) may initiate an input/output (I/O) transfer. The CPU may ascertain if a predicted time for the transfer exceeds an amount of time required to enter and exit a low-power mode and enter the low-power mode after the transfer is initiated. An I/O controller may calculate how long the transfer will take and compare that calculation to a known exit latency associated with the CPU. The calculated value is decremented by the amount of the known exit latency and the I/O controller may generate an early wake command at the decremented value. The CPU receives the early wake command and wakes such that the CPU is awake and ready to process data at conclusion of the transfer.
摘要翻译：公开了动态预测唤醒技术。中央处理单元（CPU）可以启动输入/输出（I / O）传输。 CPU可以确定传输的预测时间是否超过进入和退出低功率模式所需的时间量，并且在传输开始之后进入低功率模式。 I / O控制器可以计算传输将花费多长时间并将该计算与CPU相关的已知退出延迟进行比较。计算出的值减去已知退出延迟的数量，I / O控制器可以在递减值处生成提前唤醒命令。 CPU接收到早期唤醒命令并唤醒，以使CPU在唤醒时准备好在传输结束时处理数据。

4. 发明申请

WO2018169618A1 POWER REDUCTION VIA MEMORY EFFICIENCY COMPENSATION 审中-公开
公开(公告)号：WO2018169618A1
公开(公告)日：2018-09-20
申请号：PCT/US2018/016473
申请日：2018-02-01
申请人： QUALCOMM INCORPORATED
发明人： NAMPOOTHIRI, Sankaran , SINGH, Subodh , RANKA, Abhishek , PHILIP, Avinash
IPC分类号： G06F1/32
摘要： Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

5. 发明申请

WO2015138949A1 SYSTEMS AND METHODS FOR SUPPORTING DEMAND PAGING FOR SUBSYSTEMS IN A PORTABLE COMPUTING ENVIRONMENT WITH RESTRICTED MEMORY RESOURCES 审中-公开
标题翻译：用于支持具有限制性存储资源的便携式计算环境中的子系统的需求寻呼的系统和方法
公开(公告)号：WO2015138949A1
公开(公告)日：2015-09-17
申请号：PCT/US2015/020521
申请日：2015-03-13
申请人： QUALCOMM INCORPORATED
发明人： NAMPOOTHIRI, Sankaran , VALIAPARAMBIL, Arun , SINGH, Subodh , TOUZNI, Azzedine
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F9/45533 , G06F9/45558 , G06F12/08 , G06F13/24 , G06F13/28 , G06F2009/45575 , G06F2009/45583 , G06F2212/151 , G06F2212/171 , G06F2212/403
摘要： A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory. A first area of the primary memory is used for storing time critical code and data. A second area is available for demand pages required by a thread executing in the processor. A secondary memory is accessible to a hypervisor. The processor generates an interrupt when a page fault is detected. The hypervisor, in response to the interrupt, initiates a direct memory transfer of information in the secondary memory to the second area available for demand pages in the primary memory. Upon completion of the transfer, the hypervisor communicates a task complete acknowledgement to the processor.
摘要翻译：便携式计算设备布置有一个或多个子系统，其包括处理器和布置成在子系统级操作系统下执行线程的存储器管理单元。处理器与主存储器通信。主存储器的第一个区域用于存储时间关键代码和数据。第二个区域可用于在处理器中执行的线程所需的需求页面。管理程序可访问辅助内存。当检测到页面错误时，处理器产生中断。管理程序响应于中断，启动将辅助存储器中的信息的直接存储器传送到可用于主存储器中的需求页面的第二区域。完成传输后，管理程序将任务完成确认通知给处理器。

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