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1. 发明申请

WO2020068451A1 WIRELESS COMMUNICATION DEVICE 审中-公开
公开(公告)号：WO2020068451A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/050962
申请日：2019-09-13
申请人： QUALCOMM INCORPORATED
发明人： RONG, Sujiang , LIU, Li , SAHOTA, Gurkanwal , WANG, Kevin Hsi Huai
IPC分类号： H01Q1/24 , H01Q21/30 , H04B7/10 , H01Q21/24
摘要： A wireless communication device includes: a housing configured to retain components of the wireless communication device; an antenna unit configured to receive first free-space millimeter-wave signals and convert these signals to first electronic millimeter-wave signals; a processor disposed in the housing; and front-end circuitry communicatively coupled to the antenna unit, the front-end circuitry coupled to the processor by at least one transmission line; where the front-end circuitry is configured to: receive the first electronic millimeter-wave signals from the antenna unit; convert the first electronic millimeter-wave signals to first reduced-frequency signals each having a lower frequency than the first electronic millimeter-wave signals; and convey the first reduced-frequency signals over a same transmission line of the at least one transmission line in a multiplexed manner with different ones of the first reduced-frequency signals having different conveyance characteristics such that the different ones of the first reduced-frequency signals can be separately processed.

2. 发明申请

WO2014018893A1 SYSTEM AND METHOD OF DETERMINING AN OSCILLATOR GAIN 审中-公开
标题翻译：确定振荡器增益的系统和方法
公开(公告)号：WO2014018893A1
公开(公告)日：2014-01-30
申请号：PCT/US2013/052331
申请日：2013-07-26
申请人： QUALCOMM INCORPORATED
发明人： TANG, Yiwu , ZHU, Yunliang , NARATHONG, Chiewcharn , RONG, Sujiang
IPC分类号： H03L7/07
CPC分类号： H03L7/099 , G01R31/2832 , H03B21/01 , H03L7/07
摘要： A method includes generating a first signal based on a difference between a first frequency of a first voltage controlled oscillator (VCO) and a second frequency of a second VCO. The method further includes determining a gain of the first VCO at least partially based on the first signal.
摘要翻译：一种方法包括基于第一压控振荡器（VCO）的第一频率和第二VCO的第二频率之间的差产生第一信号。该方法还包括至少部分地基于第一信号来确定第一VCO的增益。

3. 发明申请

WO2017023479A1 LOCAL OSCILLATOR SIGNAL GENERATION CIRCUIT WITH HARMONIC CURRENT REJECTION 审中-公开
标题翻译：具有谐波电流抑制的本地振荡器信号发生电路
公开(公告)号：WO2017023479A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/041177
申请日：2016-07-06
申请人： QUALCOMM INCORPORATED
发明人： RONG, Sujiang , RANGARAJAN, Rajagopalan
IPC分类号： H03B19/14 , H03D7/14 , H03D7/18
CPC分类号： G06F1/04 , H03B19/14 , H03B27/00 , H03D7/14 , H03D7/165 , H03D7/18 , H03D2200/0088 , H03K5/01 , H03K21/026 , H03K2005/00013
摘要： A circuit (300) for generating a local oscillator signal (330out) includes: at least one divider module (320) configured to receive an input signal (342) and divide a frequency of the input signal (312) by a division ratio (340); and a load circuit (330) coupled to the at least one divider module (320), the load circuit (340) configured to provide balanced current pulses that substantially reduce at least a portion of harmonic current ripples in the local oscillator signal (330 out).
摘要翻译：用于产生本地振荡器信号（330out）的电路（300）包括：至少一个分频器模块（320），被配置为接收输入信号（342）并且将输入信号（312）的频率除以分频比（340 ）; 以及耦合到所述至少一个分频器模块（320）的负载电路（330），所述负载电路（340）被配置为提供平衡电流脉冲，其基本上减少所述本地振荡器信号（330 out）中的谐波电流纹波的至少一部分）。

4. 发明申请

WO2016204935A1 LOW POWER CURRENT RE-USING TRANSFORMER-BASED DUAL-BAND VOLTAGE CONTROLLED OSCILLATOR 审中-公开
标题翻译：低功耗电流重新使用基于变压器的双电压控制振荡器
公开(公告)号：WO2016204935A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/033620
申请日：2016-05-20
申请人： QUALCOMM INCORPORATED
发明人： FARAZIAN, Mohammad , MOSLEHI BAJESTAN, Masoud , TANG, Yiwu , PARK, Jong Min , RONG, Sujiang
IPC分类号： H03B5/12 , H03L7/099
CPC分类号： H03B5/124 , H03B5/1212 , H03B5/1215 , H03B5/1256 , H03B5/1296 , H03B2200/0072 , H03L7/099
摘要： A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnect a first output terminal of the first oscillator circuit and a first output terminal of the second oscillator circuit; a second mode switch configured to electrically connect or disconnect a second output terminal of the first oscillator circuit and a second output terminal of the second oscillator circuit; a third mode switch configured to electrically connect or disconnect a first terminal of the first inductor and a first terminal of the second inductor; and a fourth mode switch configured to electrically connect or disconnect a second terminal of the first inductor and a second terminal of the second inductor.
摘要翻译：双频带压控振荡器（VCO）包括：第一振荡器电路，包括第一电感器; 包括第二电感器的第二振荡器电路; 第一模式开关，被配置为电连接或断开第一振荡电路的第一输出端和第二振荡电路的第一输出端; 第二模式开关，被配置为电连接或断开第一振荡电路的第二输出端和第二振荡电路的第二输出端; 第三模式开关，被配置为电连接或断开第一电感器的第一端子和第二电感器的第一端子; 以及第四模式开关，被配置为电连接或断开第一电感器的第二端子和第二电感器的第二端子。

5. 发明申请

WO2014150581A1 CURRENT-MODE BUFFER WITH OUTPUT SWING DETECTOR FOR HIGH FREQUENCY CLOCK INTERCONNECT 审中-公开
标题翻译：具有高频时钟互联的输出开关检测器的电流模式缓冲器
公开(公告)号：WO2014150581A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/023684
申请日：2014-03-11
申请人： QUALCOMM INCORPORATED
发明人： PARK, Dongmin , LIU, Li , RONG, Sujiang
IPC分类号： H03K5/08 , H03K6/02
CPC分类号： H03K5/08 , H03K6/02
摘要： A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.
摘要翻译：高速电流模式时钟驱动器包括反馈电路，以将偏置节点的电压摆幅保持在限定的范围内。电流模式时钟驱动器包括在其栅极端子处接收振荡信号的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的漏极端子分别耦合到第一和第二可变电导率电路的输入端，其输出端耦合到公共节点。控制电路响应于公共节点的电压摆幅的减小而增加第一和第二可变电导率电路的电导率，并且响应于公共节点的电压摆幅的增加而降低第一和第二可变电导率电路的电导率。第一和第二可变电导率电路分别是PMOS和NMOS晶体管。

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