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1. 发明申请

WO2015126574A1 SHADER PIPELINE WITH SHARED DATA CHANNELS 审中-公开
标题翻译：具有共享数据通道的阴影管道
公开(公告)号：WO2015126574A1
公开(公告)日：2015-08-27
申请号：PCT/US2015/012917
申请日：2015-01-26
申请人： QUALCOMM INCORPORATED
发明人： MEI, Chunhui , GOEL, Vineet , KIM, Donghyun
IPC分类号： G06T15/00
CPC分类号： G06T1/60 , G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.
摘要翻译：图形处理单元（GPU）可以在图形处理流水线的至少两个阶段共享的GPU的片上图形存储器中分配共享数据信道。 GPU中的着色器单元可以执行图形处理流水线的至少两个阶段。 GPU可以在片上图形存储器的共享数据通道中存储在着色器单元上执行的图形处理流水线的至少两个阶段中的每一个生成的数据。

2. 发明申请

WO2015050681A1 GPU DIVERGENCE BARRIER 审中-公开
公开(公告)号：WO2015050681A1
公开(公告)日：2015-04-09
申请号：PCT/US2014/054966
申请日：2014-09-10
申请人： QUALCOMM INCORPORATED
发明人： MEI, Chunhui , BOURD, Alexei Vladimirovich , CHEN, Lin
IPC分类号： G06F9/52
CPC分类号： G06F9/4843 , G06F9/3887 , G06F9/522 , G06T1/20
摘要： A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.
摘要翻译：一种设备包括存储器，以及至少一个可编程处理器，其被配置为针对多个经线的每个翘曲确定布线表达式对于每个翘曲的相应线程是否为真，每个经线的暂停执行具有相应的线程，表达式是真实的，确定表达式为真的多个经线中的每一个的多个活动线程，基于多个经线中的每一个中的活动线程的数量对表达式为真的多个经线进行排序通过多个经纱中的第二扭曲的无效线程的线程数据交换多个经纱中的第一翘曲的活动线程的线程数据，并且恢复多个经线中的至少一个经线的执行，表达是真实的。

3. 发明申请

WO2015199924A1 RENDERING GRAPHICS TO OVERLAPPING BINS 审中-公开
标题翻译：渲染图形到重叠边框
公开(公告)号：WO2015199924A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/033849
申请日：2015-06-02
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan , WANG, Tao , MEI, Chunhui , ZHONG, Gang , GE, Feng
IPC分类号： G06T15/00 , G09G5/36
CPC分类号： G06T1/20 , G06T11/40 , G06T15/005 , G09G5/363 , G09G2340/0407 , G09G2360/122
摘要： In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
摘要翻译：在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或更多的像素位于图像的第一部分之外并与多个箱的第二不同仓相关联。该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。

4. 发明申请

WO2015160901A1 STOCHASTIC RASTERIZATION USING ENHANCED STENCIL OPERATIONS ON A GRAPHICS PROCESSING UNIT (GPU) 审中-公开
标题翻译：在图形处理单元（GPU）上使用增强的STENCIL操作的STOCHASTIC RASTERIZATION
公开(公告)号：WO2015160901A1
公开(公告)日：2015-10-22
申请号：PCT/US2015/025896
申请日：2015-04-15
申请人： QUALCOMM INCORPORATED
发明人： MEI, Chunhui , WANG, Tao , YEO, Young In , GOEL, Vineet
IPC分类号： G06T13/80 , G06T15/00
CPC分类号： G06T7/70 , G06T1/20 , G06T1/60 , G06T13/80 , G06T15/005 , G06T15/80 , G06T2210/12
摘要： Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.
摘要翻译：技术描述为随机光栅化。图形处理单元（GPU）可以丢弃在像素着色器处理样本之前一起指示一个或多个图元的移动的边界多边形的样本。 GPU可以利用模板缓冲区和模板测试来丢弃这样的样本。

5. 发明申请

WO2017189105A1 CONSTANT MULTIPLICATION WITH TEXTURE UNIT OF GRAPHICS PROCESSING UNIT 审中-公开
标题翻译：图形处理单元纹理单元的常量乘法
公开(公告)号：WO2017189105A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/021628
申请日：2017-03-09
申请人： QUALCOMM INCORPORATED
发明人： GRUBER, Andrew Evan , CHEN, Lin , LI, Liang , MEI, Chunhui
IPC分类号： G06T15/00 , G06T15/04
CPC分类号： G06T1/20 , G06T1/60 , G06T15/005 , G06T15/04 , G06T15/80 , G06T2200/28
摘要： A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.
摘要翻译：图形处理单元（GPU）的纹理单元可以接收纹理数据。纹理单元可以从存储器接收纹理数据。纹理单元还可以由纹理单元的乘法器电路将纹理数据乘以至少一个常数，其中该常数不与滤波操作相关联，并且其中纹理数据包括至少一个纹素。纹理单元还可以由纹理单元输出纹理数据乘以至少一个常数的结果。

6. 发明申请

WO2014120359A1 OUTPUT ORDERING OF DOMAIN COORDINATES FOR TESSELLATION 审中-公开
标题翻译：域名协调的输出命令
公开(公告)号：WO2014120359A1
公开(公告)日：2014-08-07
申请号：PCT/US2013/076655
申请日：2013-12-19
申请人： QUALCOMM INCORPORATED
发明人： MEI, Chunhui , MOEZZI MADANI, Nariman , GOEL, Vineet , CEYLAN, Usame , JIAO, Guofang
IPC分类号： G06T15/00 , G06T17/20
CPC分类号： G06T17/20 , G06T15/005
摘要： Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
摘要翻译：描述了细分的系统和方法。为了细分，镶嵌单元可以将域划分成多个部分，其中至少一个部分是连续部分。细分单元可以输出连续部分内沿着对角条纹的基元的域坐标，以增加对应于域坐标的修补坐标被存储在重用缓冲器中的可能性。

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