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1. 发明申请

WO2021118719A1 POWER MANAGEMENT CIRCUIT INCLUDING ON-BOARD CURRENT-SENSE RESISTOR AND ON-DIE CURRENT SENSOR 审中-公开
公开(公告)号：WO2021118719A1
公开(公告)日：2021-06-17
申请号：PCT/US2020/058946
申请日：2020-11-04
申请人： QUALCOMM INCORPORATED
发明人： SEVERSON, Matthew , ZOLEY, Timothy , CAO, Lipeng , CITTERELLE, Kevin Bradley , HOFMANN, Richard Gerard
IPC分类号： G01R19/165
摘要： An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

2. 发明申请

WO2014110051A1 ENHANCED DYNAMIC MEMORY MANAGEMENT WITH INTELLIGENT CURRENT/POWER CONSUMPTION MINIMIZATION 审中-公开
标题翻译：具有智能电流/功耗最小化的增强动态内存管理
公开(公告)号：WO2014110051A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010546
申请日：2014-01-07
申请人： QUALCOMM INCORPORATED
发明人： PARK, Hee Jun , HOFMANN, Richard Gerard , LEE, Yong Ju
IPC分类号： G06F1/32 , G06F12/00 , G06F13/16
CPC分类号： G06F1/3225 , G06F1/3287 , G06F13/1668 , Y02D10/171
摘要： A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.
摘要翻译：获得了多个易失性存储器件中的每个易失性存储器件的低功率状态电流/功率消耗。将数据从第一组易失性存储器件复制到第二组易失性存储器件，其中第二组易失性存储器件具有比第一组易失性存储器件低的电流/功率消耗。此外，可以为多个易失性存储器件的每一个内的每个存储器组获得电流/功率消耗。然后将数据从第一组存储器组复制到第二组存储器件中的相同存储器件中的第二组存储器组，其中第二组存储器组具有比第一组存储器更低的电流/功率消耗银行。然后将第一组易失性存储器件和/或第一组存储器组置于掉电状态。

3. 发明申请

WO2007085005A2 METHOD OF ASSOCIATING GROUPS OF CLASSIFIED SOURCE ADDRESSES WITH VIBRATION PATTERNS 审中-公开
标题翻译：使用振动模式分类分类源地址组的方法
公开(公告)号：WO2007085005A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060805
申请日：2007-01-19
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , MICHALAK, Gerald Paul , WOLFORD, Barry Joe
发明人： HOFMANN, Richard Gerard , MICHALAK, Gerald Paul , WOLFORD, Barry Joe
IPC分类号： H04M1/57 , H04M19/04
CPC分类号： H04M19/04 , H04M1/57 , H04M1/72547 , H04M19/044 , H04M19/047
摘要： In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.
摘要翻译：在会议或小组活动中，具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫，或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。为了传达这种通知，通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。当接收到通信时，基于作为分类的源地址组的成员的通信来分配组标识（ID）。便携式设备将组ID与唯一的振动模式相关联。为了提供警报，便携式设备根据独特的振动模式而振动。

4. 发明申请

WO2021203125A1 PROCESSING DATA STREAM MODIFICATION TO REDUCE POWER EFFECTS DURING PARALLEL PROCESSING 审中-公开
公开(公告)号：WO2021203125A1
公开(公告)日：2021-10-07
申请号：PCT/US2021/070327
申请日：2021-03-29
申请人： QUALCOMM INCORPORATED
发明人： PARK, Hee Jun , HOFMANN, Richard Gerard
IPC分类号： G06F9/50 , G06F13/28 , G06F9/5027 , G06F9/5066 , G06F9/5094 , G06N20/00
摘要： Certain aspects of the present disclosure provide a method for performing parallel data processing, including: receiving data for parallel processing from a data processing requestor; generating a plurality of data sub-blocks; determining a plurality of data portions in each data sub-block of the plurality of data sub-blocks; changing an order of the plurality of data portions in at least one data sub-block of the plurality of data subblocks; providing the plurality of data sub-blocks, including the at least one data subblock comprising the changed order of the plurality of data portions, to a plurality of processing units for parallel processing; and receiving processed data associated with the plurality of data sub-blocks from the plurality of processing units.

5. 发明申请

WO2016089533A1 MONITORING AND CONTROLLING BUS RING PERFORMANCE 审中-公开
标题翻译：监控和控制总线性能
公开(公告)号：WO2016089533A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/059039
申请日：2015-11-04
申请人： QUALCOMM INCORPORATED
发明人： HOFMANN, Richard Gerard , WELLS, Ryan , NAGARAJ, Vijay , NOONEY, Prudhvi Nadh
IPC分类号： H04L12/423
CPC分类号： H04L12/4013 , H04L12/423 , H04L43/16
摘要： Systems and methods for relate to bus ring performance monitoring and control. A bus ring includes an agent and a switch unit to connect the agent to the bus ring. The switch unit includes a transmit queue to store data from the bus ring to be transmitted to the agent and a receive queue to store data from the agent to be transmitted to the bus ring. A first counter is implemented to track a number of pending transactions in the transmit queue and a second counter is implemented to track a number of times the receive queue is full and unable to accept additional data. Frequency of the bus ring is increased or decreased based on comparison of values of the first counter and the second counter with corresponding predefined high and low threshold values.
摘要翻译：与总线环性能监测和控制相关的系统和方法。总线环包括代理和用于将代理连接到总线环的交换单元。交换单元包括发送队列，用于存储来自总线环的数据以发送到代理，以及接收队列，用于存储来自代理的数据以发送到总线环。实现第一计数器以跟踪发送队列中的多个待处理事务，并且实现第二计数器以跟踪接收队列已满并且不能接受附加数据的次数。基于第一计数器和第二计数器的值与相应的预定义的高和低阈值的比较来增加或减少总线环的频率。

6. 发明申请

WO2020180934A1 TICKET BASED REQUEST FLOW CONTROL 审中-公开
公开(公告)号：WO2020180934A1
公开(公告)日：2020-09-10
申请号：PCT/US2020/020896
申请日：2020-03-04
申请人： QUALCOMM INCORPORATED
发明人： MCDONALD, Joseph Gerald , DRAPALA, Garrett Michael , ROBINSON, Eric Francis , SPEIER, Thomas Philip , MAGILL, Kevin Neal , HOFMANN, Richard Gerard
IPC分类号： G06F9/50 , G06F13/16
摘要： Disclosed are ticketed flow control mechanisms in a processing system with one or more masters and one or more slaves. In an aspect, a targeted slave receives a request from a requesting master. If the targeted slave is unavailable to service the request, a ticket for the request is provided to the requesting master. As resources in the targeted slave become available, messages are broadcasted for the requesting master to update the ticket value. When the ticket value has been updated to a final value, the requesting master may re-transmit the request.

7. 发明申请

WO2012103558A1 BUS CLOCK FREQUENCY SCALING FOR A BUS INTERCONNECT AND RELATED DEVICES, SYSTEMS, AND METHODS 审中-公开
标题翻译：总线互连的总线时钟频率和相关设备，系统和方法
公开(公告)号：WO2012103558A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/023194
申请日：2012-01-30
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
发明人： HOFMANN, Richard Gerard , GANASAN, Jaya Prakash Subramaniam , LEWIS, Brandon Wayne
IPC分类号： G06F13/40 , G06F1/04 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译：公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。总线互连时钟信号对互连网络进行时钟。控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。

8. 发明申请

WO2011003083A1 TEMPERATURE COMPENSATING ADAPTIVE VOLTAGE SCALERS (AVSs), SYSTEMS, AND METHODS 审中-公开
标题翻译：温度补偿自适应电压调节器（AVS），系统和方法
公开(公告)号：WO2011003083A1
公开(公告)日：2011-01-06
申请号：PCT/US2010/040946
申请日：2010-07-02
申请人： QUALCOMM INCORPORATED , HANSQUINE, David W. , HOFMANN, Richard Gerard , MOORE, Richard Alan
发明人： HANSQUINE, David W. , HOFMANN, Richard Gerard , MOORE, Richard Alan
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variations to avoid or reduce voltage margin. In one embodiment, an AVS module is provided and coupled to a database. The database is configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and temperature level of the functional circuit(s). The AVS module may be partially or fully controllable by software that consults the database to make voltage level decisions.
摘要翻译：自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。在一个实施例中，提供AVS模块并耦合到数据库。数据库被配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。数据库允许快速的电压电平决定。在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS模块可以部分或完全由可以参考数据库的软件来控制，以进行电压电平决定。

9. 发明申请

WO2007106698A2 EFFICIENT EXECUTION OF MEMORY BARRIER BUS COMMANDS 审中-公开
标题翻译：内存障碍物总线命令的有效执行
公开(公告)号：WO2007106698A2
公开(公告)日：2007-09-20
申请号：PCT/US2007/063510
申请日：2007-03-07
申请人： QUALCOMM INCORPORATED , SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
发明人： SULLIVAN, James Edward, Jr. , GANASAN, Jaya Prakash Subramaniam , HOFMANN, Richard Gerard
IPC分类号： G06F9/38
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

10. 发明申请

WO2007101170A1 AUXILIARY WRITES OVER ADDRESS CHANNEL 审中-公开
标题翻译：地址通道辅助写
公开(公告)号：WO2007101170A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/062830
申请日：2007-02-26
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard Gerard , LOHMAN, Terry
发明人： HOFMANN, Richard Gerard , LOHMAN, Terry
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中进行通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及发送装置，被配置为在第一信道上寻址接收装置，并且从第二信道上的接收装置读取有效载荷，发送装置为还被配置为在所述第一和第三信道之间选择以将有效载荷写入所述接收设备。

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