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1. 发明申请

WO2018026555A1 VIRTUALIZED INTERNET PROTOCOL (IP) PACKET PROCESSING SYSTEM 审中-公开
标题翻译：虚拟化互联网协议（IP）分组处理系统
公开(公告)号：WO2018026555A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/043498
申请日：2017-07-24
申请人： QUALCOMM INCORPORATED
发明人： YIFRACH, Shaul, Yohai , BEN-CHEN, Tomer, Rafael , GIL, Amit , GILBOA WAIZMAN, Dan , JINDAL, Deepak
IPC分类号： H04L29/08 , H04L29/06
CPC分类号： H04L45/586 , H04L45/306 , H04L47/624 , H04L61/2521 , H04L69/22 , H04L69/321
摘要： A virtualized Internet Protocol (IP) packet processing system is provided. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.
摘要翻译：提供了一种虚拟化互联网协议（IP）分组处理系统。就这一点而言，在一个方面中，用于处理IP分组的计算电路在多个虚拟客户端之间共享。计算电路包括多个硬件功能块，每个硬件功能块被配置为执行预定义的IP包处理功能。在另一方面，为每个虚拟客户端创建虚拟信道并为其分配一个或多个硬件功能块。就这一点而言，与每个虚拟客户端相关联的IP分组可以基于指定的处理序列由相应分配的硬件功能块进行处理。通过在虚拟客户端之间共享计算电路并将相应硬件功能块分配给每个虚拟客户端，可以优化计算电路的处理效率，从而提高虚拟化IP分组处理系统的吞吐量，等待时间和功耗。 / p>

2. 发明申请

WO2018226505A1 ERROR CORRECTION CALCULATION UPON SERIAL BUS ABORT 审中-公开
公开(公告)号：WO2018226505A1
公开(公告)日：2018-12-13
申请号：PCT/US2018/035411
申请日：2018-05-31
申请人： QUALCOMM INCORPORATED
发明人： GRAIF, Sharon , BEN-CHEN, Tomer, Rafael , TOBIA, Samer
IPC分类号： G06F11/10
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/1004 , G06F13/4282
摘要： Systems, methods, and apparatus are described that enable communication of signals over a serial data bus. A method performed at a transmitter/sender device coupled to the serial data bus includes determining at a transmitter on the serial data bus a condition whereby a receiver in communication with the transmitter on the serial data bus is initiating a termination of data transfer between the transmitter and the receiver. The method further includes calculating an error check word in the transmitter simultaneous with data transfer from the transmitter to the receiver, and temporarily taking control of the serial bus with the transmitter after initiation of the termination of data transfer and transmitting the calculated error check word to the receiver.

3. 发明申请

WO2018026557A1 HARDWARE-BASED PACKET PROCESSING CIRCUITRY 审中-公开
标题翻译：基于硬件的分组处理电路
公开(公告)号：WO2018026557A1
公开(公告)日：2018-02-08
申请号：PCT/US2017/043505
申请日：2017-07-24
申请人： QUALCOMM INCORPORATED
发明人： BEN-CHEN, Tomer, Rafael , GIL, Amit , GILBOA WAIZMAN, Dan , JINDAL, Deepak , MILLER, Ayala , YIFRACH, Shaul, Yohai
IPC分类号： H04L29/08 , H04L29/06
CPC分类号： H04L69/22 , H04L45/741 , H04L45/745 , H04L69/04 , H04L69/08 , H04L69/18 , H04L69/321
摘要： Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.
摘要翻译：
提供了基于硬件的分组处理电路。在这方面，基于硬件的分组处理电路包括报头处理电路和有效载荷处理电路。基于硬件的分组处理电路以第一分组格式接收输入分组的报头部分和有效载荷部分。报头处理电路和净荷处理电路分别处理报头部分和净荷部分以形成处理的报头部分和处理后的净荷部分。基于硬件的分组处理电路基于处理的报头部分和经处理的有效负载部分以第二分组格式生成输出分组。通过在报头处理电路和有效载荷处理电路中分开处理输入分组，有可能通过专用硬件功能块来加速分组处理的选定步骤（例如，加密/解密，压缩/解压缩，校验和等）（s），因此减少了与基于软件的分组处理相关的计算资源需求和开销。

4. 发明申请

WO2022272204A1 HIGH-SPEED COMMUNICATION LINK WITH SELF-ALIGNED SCRAMBLING 审中-公开
公开(公告)号：WO2022272204A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/072506
申请日：2022-05-23
申请人： QUALCOMM INCORPORATED
发明人： BEN-CHEN, Tomer, Rafael , GRAIF, Sharon , AMARILIO, Lior
IPC分类号： H04L25/03 , H04L7/04 , H03K19/215 , H04B1/40 , H04L2007/045 , H04L25/03866 , H04L25/49 , H04L7/041 , H04W72/0466
摘要： High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

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