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1. 发明申请

WO2008059440A3 DOUBLE PATTERNING FOR LITHOGRAPHY TO INCREASE FEATURE SPATIAL DENSITY 审中-公开
标题翻译：用于光刻的双重图案增加特征空间密度
公开(公告)号：WO2008059440A3
公开(公告)日：2008-08-21
申请号：PCT/IB2007054604
申请日：2007-11-13
申请人： NXP BV , VANLEENHOVE ANJA MONIQUE , DIRKSEN PETER , VAN STEENWINCKEL DAVID , VAN DAL MARK , DOORNBOS GERBEN , JUFFERMANS CASPER
发明人： VANLEENHOVE ANJA MONIQUE , DIRKSEN PETER , VAN STEENWINCKEL DAVID , VAN DAL MARK , DOORNBOS GERBEN , JUFFERMANS CASPER
IPC分类号： G03F7/00 , G03F7/11
CPC分类号： G03F7/0035 , G03F7/11 , H01L21/0271 , H01L21/0273 , H01L21/823821 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and / or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要翻译：一种在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光刻胶层涂覆器件层; 使用第一掩模来暴露第一光致抗蚀剂; 显影第一光致抗蚀剂层以在衬底上形成第一图案; 用保护层涂覆衬底; 处理所述保护层以在其中与所述第一光刻胶接触的地方引起其中的变化，以使所述变化的保护层基本上不受后续曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆衬底; 使用第二掩模曝光第二光致抗蚀剂层; 以及显影所述第二光致抗蚀剂层以在所述衬底上形成第二图案而不显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一图案和所述第二图案一起限定具有大于每个图案中限定的特征的空间频率的散布特征第一和第二图案分开。该工艺在定义finFET器件的源极，漏极和鳍片特征方面具有特别的实用性，其特征尺寸小于通用光刻工具所能实现的特征尺寸。

2. 发明申请

WO2008007331A2 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2008007331A2
公开(公告)日：2008-01-17
申请号：PCT/IB2007052698
申请日：2007-07-09
申请人： NXP BV , SONSKY JAN , DOORNBOS GERBEN
发明人： SONSKY JAN , DOORNBOS GERBEN
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/6681
摘要： A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or "dummy fin") (40) on each side of the fin (4) serves to locally increase the thickness of the gate electrode material layer (70). In particular, as the shortest distance between each upstanding structure (40) and the respective side of the fin (4) is arranged in accordance with the invention to be less than twice the thickness of the conformal layer, the thickness of the gate electrode material layer (70) all the way across this distance between each upstanding structure (40) and the fin (4) is increased relative to that over planar regions of the substrate (2). Thus, following an anisotropic etch to remove gate electrode material (70) overlying the fin (4), some material nevertheless remains between the upstanding structures and the fin. Thus, an enlarged area of gate electrode material is formed for use as a gate contact pad.
摘要翻译：提供FinFET及其制造方法。本发明的方法提供了用于制造具有分离栅极的FinFET的优雅工艺。它与各种电介质材料和栅电极材料兼容，只要栅电极材料可以共形沉积。在鳍片（4）的每一侧上提供至少一个直立结构（或“虚拟鳍片”）（40）用于局部增加栅极电极材料层（70）的厚度。特别地，由于根据本发明将每个直立结构（40）与翅片（4）的相应侧之间的最短距离布置为小于共形层的厚度的两倍，因此栅极电极材料穿过每个直立结构（40）和鳍片（4）之间的该距离的整个层（70）相对于衬底（2）的平面区域上的距离增加。因此，在进行各向异性蚀刻以去除覆盖在鳍片（4）上的栅极电极材料（70）之后，仍然有一些材料保留在直立结构和鳍片之间。因此，栅极电极材料的扩大区域被形成以用作栅极接触焊盘。

3. 发明申请

WO2009040707A2 METHOD OF MANUFACTURING A FINFET 审中-公开
标题翻译：制造FINFET的方法
公开(公告)号：WO2009040707A2
公开(公告)日：2009-04-02
申请号：PCT/IB2008053801
申请日：2008-09-18
申请人： NXP BV , DOORNBOS GERBEN , PAWLAK BARTLOMIEJ JAN
发明人： DOORNBOS GERBEN , PAWLAK BARTLOMIEJ JAN
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a fin field effect transistor (finFET) (10) is provided wherein diffusion inhibiting species, e.g. carbon, ions are implanted from above into the extension regions (20) before spacers are formed adjacent the gate (15) and a thermal anneal is carried out to activate the source/drain dopants. The anneal conditions are selected to cause the dopant ions to diffuse from the source and drain regions (16,18) into the neighbouring extension regions (20), thus avoiding the need for a dedicated extension implant step and providing a conformal doping profile. Furthermore, by providing the diffusion inhibiting species implant, and optionally an amorphising implant to the extension regions, the rate and profile of the diffusion can be easily controlled by adjusting the anneal parameters.
摘要翻译：提供制造鳍状场效应晶体管（finFET）（10）的方法，其中扩散抑制物质例如碳离子从上面注入到延伸区域（20）中，在邻近栅极（15）形成间隔物之前，进行热退火以激活源极/漏极掺杂剂。选择退火条件以使掺杂剂离子从源极和漏极区域扩散到相邻的延伸区域（20）中，从而避免了专用扩展注入步骤的需要并提供共形掺杂分布。此外，通过提供扩散抑制物种植入物和任选地对延伸区域的非晶化植入物，可以通过调整退火参数来容易地控制扩散速率和分布。

4. 发明申请

WO2005122275A2 SEMICONDUCTOR ON INSULATOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：绝缘子半导体器件的半导体器件及其制造方法
公开(公告)号：WO2005122275A2
公开(公告)日：2005-12-22
申请号：PCT/IB2005051832
申请日：2005-06-06
申请人： KONINKL PHILIPS ELECTRONICS NV , SURDEANU RADU , DOORNBOS GERBEN , PONOMAREV YOURI , LOO JOSINE
发明人： SURDEANU RADU , DOORNBOS GERBEN , PONOMAREV YOURI , LOO JOSINE
IPC分类号： H01L21/336 , H01L29/417 , H01L29/45 , H01L29/786
CPC分类号： H01L29/78648 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78681
摘要： A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions (38, 40), activated source and drain regions (30, 32) and a body region (34). The structure may be a double gated SOI structure or a fully depleted (FD) SOI structure. A sharp intergace and low resistance are achieved with a process that uses spacers (28) and which fully replaces the full thickness of a semiconductor layer with the contact regions.
摘要翻译：半导体绝缘体上半导体器件具有金属或硅化物源极和漏极接触区域（38,40），激活的源极和漏极区域（30,32）和体区域（34）。该结构可以是双门控SOI结构或完全耗尽（FD）SOI结构。通过使用间隔物（28）并且完全用接触区域完全替代半导体层的全部厚度的工艺，实现了锐利的间隙和低电阻。

5. 发明申请

WO2007122565A2 STATIC RANDOM ACCESS MEMORY MEANS 审中-公开
标题翻译：静态随机存取存储器
公开(公告)号：WO2007122565A2
公开(公告)日：2007-11-01
申请号：PCT/IB2007051415
申请日：2007-04-19
申请人： KONINKL PHILIPS ELECTRONICS NV , NG RANICK K M , DOORNBOS GERBEN , SURDEANU RADU
发明人： NG RANICK K M , DOORNBOS GERBEN , SURDEANU RADU
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , H01L29/785
摘要： A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bitline-bar (BLB). A second pass-gate FET (T1) is coupled between a second node (B) and a bitline (BL). The second node (B) is coupled to the first pass-gate FET (T6) and the first pass- gate FET (T6) is switched according to the voltage (V B ) at the second node (B). The first node (A) is coupled to the second pass-gate FET (T1). The second pass-gate FET (T1) is switched according to the voltage (V A ) on the first node (A).
摘要翻译：提供静态随机存取存储器装置。 SRAM存储装置包括耦合在第一节点（A）和位线条（BLB）之间的第一通栅FET（T6）。第二通栅FET（T1）耦合在第二节点（B）和位线（BL）之间。第二节点（B）耦合到第一通过栅极FET（T6），并且第一通过栅极FET（T6）根据第二节点处的电压（V BAT）切换 B）。第一节点（A）耦合到第二通过栅极FET（T1）。第二栅极FET（T1）根据第一节点（A）上的电压（V SUB）来切换。

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