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1. 发明申请

WO2008018035A3 METHODS AND PRODUCTS FOR DETERMINING AND VISUALIZIN IC BEHAVIOUR 审中-公开
标题翻译：测定和可视化IC行为的方法和产品
公开(公告)号：WO2008018035A3
公开(公告)日：2009-11-05
申请号：PCT/IB2007053139
申请日：2007-08-08
申请人： NXP BV , RUTTEN MARTIJN J
发明人： RUTTEN MARTIJN J
IPC分类号： G06F11/32 , G06F11/34
CPC分类号： G06F11/3466 , G06F11/323 , G06F2201/835 , G06F2201/86
摘要： A method (100) is disclosed for determining the behaviour of an integrated circuit comprising a plurality of resources and being configured to execute a plurality of operations that each require temporary allocation and deallocation of at least a subset of the plurality of resources during said execution. The method comprises the steps of monitoring (130) the execution of at least some of the plurality of operations during an execution run of the IC, capturing (140) events indicating the (de)allocation of resources during said execution, capturing events (150) indicating an operational relationship between allocated resources during said execution, assigning (140, 150) a time stamp to each event; and making (160) the captured events available for visualization. This facilitates the visualization of events that are interrelated in terms of the operation to which they are assigned at a given time instant. This visualization may be realized in the form of a connectivity graph, for which another method (200) is disclosed.
摘要翻译：公开了一种用于确定包括多个资源的集成电路的行为的方法（100），并且被配置为执行多个操作，每个操作在所述执行期间需要对所述多个资源的至少一个子集进行临时分配和释放。该方法包括以下步骤：在IC执行期间监视（130）执行多个操作中的至少一些操作，捕获（140）指示在所述执行期间（de）资源分配的事件，捕获事件（150））指示在所述执行期间分配的资源之间的操作关系，向每个事件分配（140,150）时间戳; 并且（160）捕获的事件可用于可视化。这有助于可视化在给定时间点分配给它们的操作方面相互关联的事件。该可视化可以以连接图的形式来实现，对于该连接图公开了另一种方法（200）。

2. 发明申请

WO2004079488A3 DATA PROCESSING SYSTEM WITH CACHE OPTIMISED FOR PROCESSING DATAFLOW APPLICATIONS 审中-公开
标题翻译：具有优化处理数据流应用的缓存的数据处理系统
公开(公告)号：WO2004079488A3
公开(公告)日：2005-07-28
申请号：PCT/IB2004050150
申请日：2004-02-25
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
发明人： VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
IPC分类号： G06F12/08
CPC分类号： G06F12/084
摘要： Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises selecting means (350) for selecting locations for storing elements of a data stream in said cache memory (200) in accordance to said stream identification (stream_id).
摘要翻译：为每个数据流保留非重叠缓存位置。因此，每个流唯一的流信息用于对高速缓冲存储器进行索引。这里，流信息由流标识表示。特别地，提供了优化用于处理具有任务和数据流的数据流应用的数据处理系统，其中不同流竞争共享高速缓存资源。明确的流识别与每个所述数据流相关联。所述数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个所述处理器）和用于控制所述高速缓冲存储器（200）的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓存存储器（200）中的每一个相关联。所述缓存控制器（300）包括选择装置（350），用于根据所述流标识（stream_id）选择用于存储所述高速缓冲存储器（200）中的数据流元素的位置。

3. 发明申请

WO2004079489A3 DATA PROCESSING SYSTEM WITH PREFETCHING MEANS 审中-公开
标题翻译：具有预先设计的数据处理系统
公开(公告)号：WO2004079489A3
公开(公告)日：2005-07-28
申请号：PCT/IB2004050151
申请日：2004-02-25
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
发明人： VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.
摘要翻译：预测不预期会被进一步使用的缓存数据的解除，而不是预测未来的I / O操作，然后从主存储器中取出数据以替换高速缓存中的被解除的数据。因此，首先识别包含期望不被进一步使用的数据的高速缓冲存储器中的位置，然后执行预取操作以便请求新数据以将高速缓冲存储器中的上述位置重新填充。因此，数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块（210）的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个的所述处理器（12）以及用于将数据预取到所述高速缓冲存储器（200）中的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓冲存储器（200）中的每一个相关联。所述高速缓存控制器（300）包括用于识别所述高速缓冲存储器（200）中的至少一个位置的确定装置（350），其包含被预测为无需罚款的第一数据，以及用于发出预取操作的预取装置（320）所述位置处的第一数据具有适合所述位置的第二数据。

4. 发明申请

WO2004077206A2 DATA PROCESSING SYSTEM HAVING A PLURALITY OF PROCESSING ELEMENTS, A METHOD OF CONTROLLING A DATA PROCESSING SYSTEM HAVING A PLURALITY OF PROCESSING ELEMENTS 审中-公开
标题翻译：具有多种加工元素的数据处理系统，一种控制具有多种加工元素的数据处理系统的方法
公开(公告)号：WO2004077206A2
公开(公告)日：2004-09-10
申请号：PCT/IB2004050124
申请日：2004-02-18
申请人： KONINKL PHILIPS ELECTRONICS NV , RUTTEN MARTIJN J , VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT-JAN D
发明人： RUTTEN MARTIJN J , VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT-JAN D
IPC分类号： G06F1/00 , G06F9/44 , G06F9/46 , G06F
CPC分类号： G06F9/4436 , G06F9/52
摘要： The invention relates to task management in a data processing system, having a plurality of processing elements (CPU, ProcA, ProcB, ProcC). Therefore a data processing system is provided, comprising at least a first processing element (CPU, ProcA, ProcB, ProcC) and a second processing element (CPU, ProcA, ProcB, ProcC) for processing a stream of data objects (DS_Q, DS R, DS S, DST), the first processing element being arranged to pass data objects from the stream of data objects to the second processing element. The first and the second processing element are arranged for parallel execution of an application comprising a set of tasks (TP, TA, TB 1, TB2, TC), and the first and the second processing element are arranged to be responsive to the receipt of a unique identifier. In order to ensure integrity of data during reconfiguration of the application, the unique identifier is inserted into the data stream and passed from one processing element to the other. Application reconfiguration is performed when the corresponding processing element receives the unique identifier, and as a result global application control is allowed at a unique location in the data space.
摘要翻译：本发明涉及具有多个处理元件（CPU，ProcA，ProcB，ProcC）的数据处理系统中的任务管理。因此，提供了一种数据处理系统，其至少包括用于处理数据对象流（DS_Q，DSR）的至少第一处理元件（CPU，ProcA，ProcB，ProcC）和第二处理元件（CPU，ProcA，ProcB，ProcC），DS S，DST），第一处理元件被布置成将数据对象从数据对象流传递到第二处理元件。第一处理单元和第二处理单元被布置为用于并行执行包括一组任务（TP，TA，TB1，TB2，TC）的应用，并且第一和第二处理单元被布置成响应于唯一标识符。为了确保在重新配置应用期间数据的完整性，将唯一标识符插入到数据流中，并从一个处理元件传递到另一个处理元件。当对应的处理单元接收到唯一标识符时执行应用重新配置，从而在数据空间中的唯一位置允许全局应用控制。

5. 发明申请

WO03052586A2 DATA PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND A COMMUNICATION MEANS IN A DATA PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS 审中-公开
标题翻译：具有多个处理器的数据处理系统和具有多个处理器的数据处理系统中的通信手段
公开(公告)号：WO03052586A2
公开(公告)日：2003-06-26
申请号：PCT/IB0205168
申请日：2002-12-05
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT J , RUTTEN MARTIJN J , VAN DER WOLF PIETER , GANGWAL OM P
发明人： VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT J , RUTTEN MARTIJN J , VAN DER WOLF PIETER , GANGWAL OM P
IPC分类号： G06F9/38 , G06F9/00 , G06F9/46 , G06F15/16
CPC分类号： G06F9/54
摘要： The invention is based on the idea to effectively separate communication hardware, e.g. busses and memory, and computation hardware, e.g. processors, in a data processing system by introducing a communication means for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication means provide the communication support for the respective processor. Therefore, a data processing system is provided with a computation, a communication support and a communication network layer. The computation layer comprises a first and at least a second processor for processing a stream of data objects. The first processor passes a number of data objects from a stream to the second processor which can then process the data objects. The communication network layer includes a memory and a communication network for linking the first processor and the second processors with said memory. The communication support layer is arranged between the computation layer and the communication network layer and comprises one communication means for each second processor in the computation layer. The communication means of each of the second processors controls the communication between the said second processor and the memory via the communication network in the communication network layer.
摘要翻译：本发明基于有效分离通信硬件的想法，例如，总线和存储器，以及计算硬件，例如。处理器，通过引入每个处理器的通信装置在数据处理系统中。通过引入这种分离，处理器可以专注于执行其功能特定任务，而通信意味着为相应的处理器提供通信支持。因此，向数据处理系统提供计算，通信支持和通信网络层。计算层包括用于处理数据对象流的第一和至少第二处理器。第一处理器将许多数据对象从流传递到第二处理器，然后可以处理数据对象。通信网络层包括用于将第一处理器和第二处理器与所述存储器链接的存储器和通信网络。通信支持层被布置在计算层和通信网络层之间，并且包括用于计算层中的每个第二处理器的一个通信装置。每个第二处理器的通信装置经由通信网络层中的通信网络来控制所述第二处理器和存储器之间的通信。

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