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1. 发明申请

WO2008032261A3 DEINTERLEAVER FOR A MULTI-STAGE INTERLEAVING SCHEME WITH PROCESSING OF BIT PAIRS 审中-公开
标题翻译：用于处理位对的多级交互方案的消除器
公开(公告)号：WO2008032261A3
公开(公告)日：2008-05-22
申请号：PCT/IB2007053643
申请日：2007-09-10
申请人： NXP BV , PU TIANYAN , SAWITZKI SERGEI V
发明人： PU TIANYAN , SAWITZKI SERGEI V
IPC分类号： H03M13/27
CPC分类号： H03M13/2796 , H03M13/271 , H03M13/276
摘要： A deinterleaver (10) for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means (12) for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory (16,18) for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator (20) for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.
摘要翻译：提供了一种用于无线通信设备的解交织器（10），其实现简单且便宜。特别地，提供了一种解交织器，用于对表示使用多级交织方案交织的多个符号的数据比特流进行解交织，所述解交织器包括用于将流中的数据比特排列成对的预处理装置（12）使得该对中的数据位是来自符号的连续数据位; 至少一个用于存储所述配对位的存储器（16,18），使得每对数据位被存储在所述存储器中的相应位置中; 以及用于所述至少一个存储器的读取和写入地址生成器（20），所述发生器适于确定所述至少一个存储器中的数据位对将被存储的地址，并且至少确定所述地址一个要读取的数据位对的存储器。

2. 发明申请

WO2006109240A3 FAST FOURIER TRANSFORM ARCHITECTURE 审中-公开
标题翻译：快速FOURIER变形架构
公开(公告)号：WO2006109240A3
公开(公告)日：2009-09-03
申请号：PCT/IB2006051101
申请日：2006-04-11
申请人： NXP BV , PU TIANYAN , BI LEI , TJIA JEROME
发明人： PU TIANYAN , BI LEI , TJIA JEROME
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.
摘要翻译：最后一个傅立叶变换架构具有并行数据处理路径。输入数据以重复序列应用于并行数据处理路径，并以这些路径进行处理。数据定序器用于将来自数据处理路径的输出组合到所需的序列中。

3. 发明申请

WO2008041160A3 METHOD AND APPARATUS FOR GENERATING DATA PACKETS FOR TRANSMISSION IN AN OFDM COMMUNICATION SYSTEM 审中-公开
标题翻译：用于在OFDM通信系统中生成用于传输的数据分组的方法和装置
公开(公告)号：WO2008041160A3
公开(公告)日：2008-06-26
申请号：PCT/IB2007053933
申请日：2007-09-27
申请人： NXP BV , PU TIANYAN
发明人： PU TIANYAN
IPC分类号： H04L27/26 , H04B1/69
CPC分类号： H04L27/2626 , H04L27/2602 , H04W52/0212 , Y02D70/00 , Y02D70/142 , Y02D70/144 , Y02D70/168
摘要： Method and apparatus for generating data packets for transmission in an orthogonal frequency division modulated communication system, in which preamble sequence for each packet is generated in the frequency domain or the time domain depending on at least two conditions to save power consumption and enable implementation in a single CMOS chip.
摘要翻译：用于在正交频分调制通信系统中生成用于发送的数据分组的方法和装置，其中根据至少两个条件在频域或时域中生成每个分组的前同步码序列，以节省功耗并使其能够实现单CMOS芯片。

4. 发明申请

WO2006103601A2 CANONICAL SIGNED DIGIT MULTIPLIER 审中-公开
标题翻译：经典签名数字乘法器
公开(公告)号：WO2006103601A2
公开(公告)日：2006-10-05
申请号：PCT/IB2006050892
申请日：2006-03-23
申请人： KONINKL PHILIPS ELECTRONICS NV , PU TIANYAN , BI LEI
发明人： PU TIANYAN , BI LEI
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.
摘要翻译：乘数能够以CSD形式将输入数据值乘以选定的常数值。所选择的常数值具有多个位对，并且乘法器包括多路复用器，每个由多个选择的常数值的相应位组控制。每个多路复用器具有多个输入，并且被连接以接收输入数据值，输入数据值的倒数和所述输入上的全零，并且它被控制成使得其输出输入数据值，取决于所选常数值的相应位对的值，输入数据值的倒数或全零。可变移位块各自被连接以接收来自所述多路复用器中的相应一个的输入，并且各自适于根据相应的位对的值将其接收到的输入移位第一位移位值或第二位移位值其中所述第一位移位值和所述第二位移位值相差1.所述乘法器还包括组合电路，用于接收来自所述多个移位块的输出，并且用于组合来自所述多个移位的输出块并且进一步进行位移，以形成等于将输入数据值乘以选定常数值的结果的输出值。

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