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1. 发明申请

WO2009010919A3 DONGLE FOR FUNCTIONALLY TESTING AN ELECTRONIC DEVICE 审中-公开
公开(公告)号：WO2009010919A3
公开(公告)日：2009-01-22
申请号：PCT/IB2008/052833
申请日：2008-07-15
申请人： NXP B.V. , BAUER, Harald , FULCHERI, Patrick , PERRIN, Jean-Philippe
发明人： BAUER, Harald , FULCHERI, Patrick , PERRIN, Jean-Philippe
IPC分类号： G06F21/00
摘要： A dongle (110) for functionally testing an electronic device (120), wherein the dongle (110) comprises a device interface (111) adapted for a communicative connection with the electronic device (120), and a device communication unit (112) adapted for exchanging communication messages with an electronic device (120) being communicatively connected to the device interface (111) in such a manner that execution of a functional test for analyzing a function of the electronic device (120) is selectively enabled when the electronic device (120) is communicatively connected to the device interface (111).

2. 发明申请

WO2006067729A1 INTEGRATED CIRCUIT WITH IMPROVED DEVICE SECURITY 审中-公开
标题翻译：具有改进的设备安全性的集成电路
公开(公告)号：WO2006067729A1
公开(公告)日：2006-06-29
申请号：PCT/IB2005/054314
申请日：2005-12-19
申请人： PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH , KONINKLIJKE PHILIPS ELECTRONICS N. V. , FULCHERI, Patrick , BAUER, Harald N. , PERRIN, Jean-Philippe
发明人： FULCHERI, Patrick , BAUER, Harald N. , PERRIN, Jean-Philippe
IPC分类号： G06F21/00
CPC分类号： G06F21/85 , G06F12/1425 , G06F12/1491 , G06F21/79
摘要： A semiconductor device having circuitry comprising an embedded memory, an embedded processor for executing application codes, and a functional hardware element coupled with the embedded memory via a protected bus, and with the embedded processor via an unprotected bus, the hardware element being arranged to protect the protected bus, and including a locking means comprising at least one lock bit for globally locking at least part of the locking means before executing the application code.
摘要翻译：一种具有电路的半导体器件，包括嵌入式存储器，用于执行应用代码的嵌入式处理器，以及经由受保护总线与嵌入式存储器耦合的功能硬件元件，以及经由未受保护总线与嵌入式处理器相连接的硬件元件，保护总线，并且包括锁定装置，该锁定装置包括至少一个锁定位，用于在执行应用代码之前全局地锁定锁定装置的至少一部分。

3. 发明申请

WO2007015204A2 A SECURE TERMINAL, A ROUTINE AND A METHOD OF PROTECTING A SECRET KEY 审中-公开
标题翻译：安全终端，方法和保护秘密钥匙的方法
公开(公告)号：WO2007015204A2
公开(公告)日：2007-02-08
申请号：PCT/IB2006/052616
申请日：2006-08-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PERRIN, Jean-Philippe , BAUER, Harald , FULCHERI, Patrick
发明人： PERRIN, Jean-Philippe , BAUER, Harald , FULCHERI, Patrick
IPC分类号： G06F21/62 , G06F21/71 , G06F21/73
CPC分类号： G06F21/73 , G06F21/6209 , G06F21/71 , G06F2221/2143 , G06F2221/2149
摘要： The method of protecting a secret key from being read by a non-secure software application, comprises a step (94) of recording the secret key as a routine stored in an executable-only memory. The routine having: load instructions to load the secret key into a memory readable by a secure and a non-secure software application, if the routine is called by the secure software application, and control instructions to leave only dummy data instead of the secret key in the readable memory if the software application calling the executable-only routine is the non-secure software application.
摘要翻译：保护秘密密钥不被非安全软件应用程序读取的方法包括将秘密密钥记录为存储在可执行的存储器中的程序的步骤（94）。该程序具有：加密指令以将秘密密钥加载到由安全和非安全软件应用程序读取的存储器中，如果该程序由安全软件应用程序调用，并且控制指令仅留下伪数据而不是秘密密钥在可读存储器中，如果调用可执行程序例程的软件应用程序是非安全软件应用程序。

4. 发明申请

WO2007054871A3 CONTROL DEVICE WITH FLAG REGISTERS FOR SYNCHRONIZATION OF COMMUNICATIONS BETWEEN CORES 审中-公开
公开(公告)号：WO2007054871A3
公开(公告)日：2007-05-18
申请号：PCT/IB2006/054104
申请日：2006-11-03
申请人： NXP B.V. , CHANCEL, Francois , FULCHERI, Patrick
发明人： CHANCEL, Francois , FULCHERI, Patrick
IPC分类号： G06F15/167
摘要： A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BCl, BC2), to a memory (M) arranged to store data to be transferred between these cores (Cl, C2). This control device (D) comprises at least one flag register (FRl, FR2) coupled to the cores (C1,C2) via the buses (BCl, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1,C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.

5. 发明申请

WO2006013498A1 DATA PROCESSING DEVICE ADAPTABLE TO VARIABLE EXTERNAL MEMORY SIZE AND ENDIANESS 审中-公开
标题翻译：数据处理设备适用于可变外部存储器尺寸和可靠性
公开(公告)号：WO2006013498A1
公开(公告)日：2006-02-09
申请号：PCT/IB2005/052402
申请日：2005-07-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , FULCHERI, Patrick , CHANCEL, François
发明人： FULCHERI, Patrick , CHANCEL, François
IPC分类号： G06F13/40
CPC分类号： G06F13/4013 , G06F13/4018
摘要： A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage.
摘要翻译：数据处理装置（D）包括外部存储器（EM），用于存储以端部形式定义程序的至少一部分的数据，以及通过存储器总线连接到外部存储器（EM）的集成电路（IC）（MB），并且包括i）适于运行该程序的嵌入式处理器（EP），ii）用于存储该程序的至少一个引导代码的内部存储器（IM），iii）外部存储器接口（EMI）连接到存储器总线（MB），以及iv）将内部存储器（IM）和外部存储器接口（EMI）连接到嵌入式处理器（EP）的处理器总线（PB）。外部存储器（EM）还在所选择的地址处存储具有表示其大小（等于N / 8位）的值的N位数据字（C）以及存储的程序数据的Endian形式。数据处理设备（D）还包括耦合到嵌入式处理器（EP）和外部存储器接口（EMI）的配置装置（CM），并且被配置为从该N位数据的8位的至少一部分推导出字（C），由外部存储器接口在外部存储器（EM）的选定地址读取，外部存储器的大小和端部存储形式，以及根据外部存储器接口（EMI）的宽度设置根据推断的Endian形式的存储，推断出嵌入式处理器（EP）的外部存储器尺寸和数据处理模式。

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