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1. 发明申请

WO2019092425A1 TRANSMISSION GATES 审中-公开
公开(公告)号：WO2019092425A1
公开(公告)日：2019-05-16
申请号：PCT/GB2018/053239
申请日：2018-11-08
申请人： NORDIC SEMICONDUCTOR ASA , SAMUELS, Adrian James
发明人： WU, Hsin-Ta
IPC分类号： H03K17/0812
CPC分类号： H03K17/08122 , H03K2217/0054
摘要： A transmission gate circuit portion (8) is arranged selectively to pass an input signal V in from an input node to an output node. A control circuit portion (11) arranged to provide a first control voltage V supply / 0 V and a second control voltage 0 V / V in . A first field-effect-transistor (10) has its drain terminal connected to the input node, its source terminal connected to the output node, and its gate terminal connected to the first control voltage V supply / 0 V. A second field-effect-transistor (12) has its drain terminal connected to the output node, its source terminal connected to the input node, and its gate terminal connected to the second control voltage 0 V / V in . The drain-source breakdown voltages of the two transistors (10), (12) are substantially equal. At least one of the first and second field-effect transistors (10), (12) has its respective drain-source breakdown voltage greater than its respective gate-source, gate-drain, and gate-body breakdown voltages of the respective field-effect- transistor (10), (12).

2. 发明申请

WO2022106649A1 AMPLITUDE REGULATOR FOR CRYSTAL OSCILLATOR 审中-公开
公开(公告)号：WO2022106649A1
公开(公告)日：2022-05-27
申请号：PCT/EP2021/082356
申请日：2021-11-19
申请人： NORDIC SEMICONDUCTOR ASA
发明人： WU, Hsin-Ta
IPC分类号： H03B5/36
摘要： An amplitude regulator circuit portion (208) is arranged to supply a current to an inverter (206) in an oscillator circuit (204). The regulator (208) monitors a voltage at the input terminal of the inverter (206) and varies the current supplied to the inverter (206) in response to the monitored voltage. The amplitude regulator (208) comprises first, second, and third PMOS transistors (P1-3), and first and second NMOS transistors (N1-2) and is arranged such that an input node of the amplitude regulator (208) is connected to the input terminal of the inverter (206), a respective gate terminal of each of the first and second NMOS transistors (N1-2), and a respective drain terminal of each of the first NMOS transistor (N1) and first PMOS transistor (P1). The amplitude regulator (208) also comprises a back-bias circuit portion (212) arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor (N2), thereby varying a threshold voltage of said second NMOS transistor (N2), where the threshold voltage of the second NMOS transistor (N2) is lower than the threshold voltage of the first NMOS transistor (N1).

3. 发明申请

WO2022079086A1 CONSTANT-GM CURRENT SOURCE 审中-公开
公开(公告)号：WO2022079086A1
公开(公告)日：2022-04-21
申请号：PCT/EP2021/078278
申请日：2021-10-13
申请人： NORDIC SEMICONDUCTOR ASA
发明人： WU, Hsin-Ta
IPC分类号： H03B5/36 , G05F3/24 , G05F3/26
摘要： A constant-gm current source (102), arranged to generate a supply current (IPIERCE) for a Pierce oscillator. First (P1) and second (N1) transistors have their source terminals connected to first (AVDD) and second (GND) supply rails respectively, and their drain terminals are connected together and to the gate terminal of the first transistor (P1). Third (P2) and fourth (N2) transistors have their source terminals are connected to the first (AVDD) and second (GND) supply rails respectively, and their drain terminals are connected together and to the gate terminal of the fourth transistor (N2). An output portion (N3, P4, P5) varies the supply current (IPIERCE) in response to a voltage at the drain terminals of the third and fourth transistors (P2, N2). The gate terminals of the first (P1) and third (P2) transistors are connected together and receive a gate voltage (vgp), and the gate terminals of the second (N1) and fourth (N2) transistors are connected together. A reference resistive element (R1') connected between the source terminal of the third transistor (P2) and the first supply rail (AVDD) has a predetermined resistance value. An auto-calibration transistor (R2, P6) has its source terminal connected to the first supply rail (AVDD) and its drain terminal connected to the source terminal of the first transistor (P1). The gate terminal of the auto-calibration transistor (R2, P6) is supplied with the gate voltage (vgp).

4. 发明申请

WO2022106617A1 AMPLITUDE REGULATOR FOR CRYSTAL OSCILLATOR 审中-公开
公开(公告)号：WO2022106617A1
公开(公告)日：2022-05-27
申请号：PCT/EP2021/082297
申请日：2021-11-19
申请人： NORDIC SEMICONDUCTOR ASA
发明人： STRANDVIK, Erlend , WU, Hsin-Ta
IPC分类号： H03B5/36
摘要： An electronic device (202) comprises an oscillator circuit portion (204) comprising an inverter (206) and a crystal oscillator connected between the input and output terminals of the inverter (XC1, XC2). An amplitude regulator circuit portion (208) is arranged to supply a current to the inverter (206). The amplitude regulator (208) monitors a voltage at the input of the inverter (206) and varies the current supplied to the inverter (206) in response to the monitored voltage. The amplitude regulator (208) comprises a trimmable resistor (R1') arranged such that the voltage at the input of the inverter (206) is set to an operating point when the supply current provided by the amplitude regulator circuit (208) is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor (R1'). A current monitor (210) is arranged to monitor the current supplied to the inverter (206) during operation and to determine therefrom whether the voltage at the input terminal of the inverter (206) is within a predetermined range.

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