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1. 发明申请

WO9802967A3 A DELAY ESTIMATION METHOD AND A RECEIVER 审中-公开
标题翻译：延迟估计方法和接收器
公开(公告)号：WO9802967A3
公开(公告)日：1998-02-26
申请号：PCT/FI9700446
申请日：1997-07-11
申请人： NOKIA MOBILE PHONES LTD , LILLEBERG JORMA , NIEMINEN ESKO
发明人： LILLEBERG JORMA , NIEMINEN ESKO
IPC分类号： H04B1/707 , H04B7/02 , H04B
CPC分类号： H04B1/707
摘要： The invention relates to a delay estimation method and a receiver in a radio system. The signals originate from one or several transmitters and they have propagated along several paths. In the method, one of the determined paths (73 - 77) is selected at a time for estimation. The least squares minimization problem between the received signal and the code bank model is solved path by path (73 - 77) and delay by delay. In such a case, when the minimization results are formed, the delay of only one selected path is changed at a time while the delays of the other paths (73 - 77) remain unchanged. The minimization results are used to search for a delay for which the minimized result is at most equal to the results for the other delays. This delay is stored and used as the constant value of the path (73 - 77) when the delays of the other paths are searched for. The method can be repeated if necessary. The method has the advantage that it provides the delays of all the paths (73 - 77) of all the users simultaneously without information on the user symbols or the attenuation coefficients of the channel.

2. 发明申请

WO2010001239A3 ADDRESS GENERATION FOR MULTIPLE ACCESS OF MEMORY 审中-公开
标题翻译：存储器多次访问地址生成
公开(公告)号：WO2010001239A3
公开(公告)日：2010-04-15
申请号：PCT/IB2009006145
申请日：2009-07-02
申请人： NOKIA CORP , NIEMINEN ESKO
发明人： NIEMINEN ESKO
IPC分类号： G06F12/08 , H03M13/29
CPC分类号： H04L49/901 , G06F9/345 , G06F9/3885 , G06F12/0607 , H03M13/276 , H03M13/2775 , H03M13/2957 , H03M13/6505 , H03M13/6566 , H04L47/14 , H04L49/90 , H04L49/9047 , Y02D10/13
摘要： A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32,... This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.
摘要翻译：存储体具有多个存储器。在一个实施例中，前向单元以前向双向访问顺序将逻辑存储器地址应用于存储体，后向单元以向后双向访问顺序向存储体提供逻辑存储器地址，以及半蝶形网络（至少一半，和8元组实施例中的桶形移位器）被布置在存储体和前向单元和后向单元之间。生成一组控制信号，这些控制信号被施加到一半或更多个蝶形网络（以及当前的桶形移位器），以便在第一种情况下以线性顺序以n元组并行性访问存储体，第二个实例中的二次多项式顺序，其中n = 2,4,8,16,32，...此访问用于逻辑地址的任何n元组，并且没有存储器访问冲突。以这种方式，存储器访问可以被控制数据解码。

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