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1. 发明申请

WO2019046104A1 WEAR LEVELING FOR RANDOM ACCESS AND FERROELECTRIC MEMORY 审中-公开
公开(公告)号：WO2019046104A1
公开(公告)日：2019-03-07
申请号：PCT/US2018/047790
申请日：2018-08-23
申请人： MICRON TECHNOLOGY, INC.
发明人： FACKENTHAL, Richard E. , VIMERCATI, Daniele , MILLS, Duane R.
IPC分类号： G11C11/22
摘要： Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

2. 发明申请

WO2023076248A1 MEMORY CELL AND WRAPPED DATA LINE STRUCTURE 审中-公开
公开(公告)号：WO2023076248A1
公开(公告)日：2023-05-04
申请号：PCT/US2022/047701
申请日：2022-10-25
申请人： MICRON TECHNOLOGY, INC.
发明人： KARDA, Kamal M. , CARMAN, Eric S. , SARPATWARI, Karthik , RAMASWAMY, Durai Vishak Nirmal , FACKENTHAL, Richard E. , LIU, Haitao
IPC分类号： H10B12/00 , H01L29/788
摘要： Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

3. 发明申请

WO2023009333A1 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE GATES 审中-公开
公开(公告)号：WO2023009333A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/037309
申请日：2022-07-15
申请人： MICRON TECHNOLOGY, INC.
发明人： CARMAN, Eric S. , RAMASWAMY, Durai Vishak Nirmal , FACKENTHAL, Richard E. , KARDA, Kamal M. , SARPATWARI, Karthik , LIU, Haitao , MILLS, Duane R. , CAILLAT, Christian
IPC分类号： H01L27/108 , H01L29/423 , H01L29/788
摘要： Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated, from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

4. 发明申请

WO2017156028A2 PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE 审中-公开
标题翻译：并行访问技术在内存部分通过部分独立
公开(公告)号：WO2017156028A2
公开(公告)日：2017-09-14
申请号：PCT/US2017/021199
申请日：2017-03-07
申请人： MICRON TECHNOLOGY, INC.
发明人： FACKENTHAL, Richard E.
IPC分类号： G11C11/22
摘要： A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
摘要翻译：具有诸如铁电存储器单元（混合RAM（HRAM）单元）的多个存储器单元部分的存储器设备可以提供对存储器器件的独立部分内的存储器单元的并行访问。第一存储器单元可以被激活，并且可以确定第二存储器单元独立于第一存储器单元。如果第二存储器单元独立于第一存储器单元，则可以在第一存储器单元的操作结束之前激活第二存储器单元。存储器部分处的锁存硬件可以锁存存储器部分处的地址，以便允许将新地址提供给不同部分以访问第二存储器单元。

5. 发明申请

WO2023076261A1 VERTICAL MEMORY CELL AND CONDUCTIVE SHIELD STRUCTURE 审中-公开
公开(公告)号：WO2023076261A1
公开(公告)日：2023-05-04
申请号：PCT/US2022/047720
申请日：2022-10-25
申请人： MICRON TECHNOLOGY, INC.
发明人： KARDA, Kamal M. , FACKENTHAL, Richard E. , RAMASWAMY, Durai Vishak Nirmal
IPC分类号： H10B12/00 , G11C11/4097 , G11C8/14 , H01L29/788
摘要： Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.

6. 发明申请

WO2022182838A1 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 审中-公开
公开(公告)号：WO2022182838A1
公开(公告)日：2022-09-01
申请号：PCT/US2022/017653
申请日：2022-02-24
申请人： MICRON TECHNOLOGY, INC.
发明人： KARDA, Kamal M. , LIU, Haitao , SARPATWARI, Karthik , RAMASWAMY, Durai Vishak Nirmal , CALDERONI, Alessandro , FACKENTHAL, Richard E. , MILLS, Duane R.
IPC分类号： H01L27/108 , H01L29/78
摘要： Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

7. 发明申请

WO2019027727A1 WEAR LEVELING 审中-公开
公开(公告)号：WO2019027727A1
公开(公告)日：2019-02-07
申请号：PCT/US2018/043414
申请日：2018-07-24
申请人： MICRON TECHNOLOGY, INC.
发明人： FACKENTHAL, Richard E. , MILLS, Duane R.
IPC分类号： G06F12/02 , G11C16/34
摘要： An example apparatus comprises a first portion of an array of memory cells, a second portion of the array of memory cells, a first register corresponding to the first portion, and a second register corresponding to the second portion. The first register is to indicate whether the first portion is to be wear leveled based on how often the first portion is or is to be accessed, and the second register is to indicate whether the second portion is to be wear leveled based on how often the second portion is or is to be accessed. The apparatus is to set the first or second register to indicate whether the first or second portion is to be wear leveled in response to a setup command. And the apparatus is to receive the setup command when the apparatus powers up.

8. 发明申请

WO2019040495A1 ON DEMAND MEMORY PAGE SIZE 审中-公开
公开(公告)号：WO2019040495A1
公开(公告)日：2019-02-28
申请号：PCT/US2018/047328
申请日：2018-08-21
申请人： MICRON TECHNOLOGY, INC.
发明人： MILLS, Duane R. , FACKENTHAL, Richard E.
IPC分类号： G06F13/16 , G06F3/06 , G06F12/02
摘要： Systems, devices, and methods related to on demand memory page size are described. A memory system may employ a protocol that supports on demand variable memory page sizes. A memory system may include one or more non-volatile memory devices that may each include a local memory controller configured to support variable memory page size operation. The memory system may include a system memory controller that interfaces between the non-volatile memory devices and a processor. The system memory controller may, for instance, use a protocol that facilitates on demand memory page size where a determination of a particular page size to use in an operation may be based on characteristics of memory commands and data involved in the memory command.

9. 发明申请

WO2018071101A1 TEMPERATURE UPDATE FOR A MEMORY DEVICE 审中-公开
标题翻译：存储设备的温度更新
公开(公告)号：WO2018071101A1
公开(公告)日：2018-04-19
申请号：PCT/US2017/048647
申请日：2017-08-25
申请人： MICRON TECHNOLOGY, INC.
发明人： FACKENTHAL, Richard E.
IPC分类号： G11C7/04 , G11C11/22
摘要： Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.
摘要翻译：描述了用于操作一个或多个铁电存储器单元的方法，系统和设备，并且更具体地描述了用于存储器设备的温度更新。存储器阵列可以根据包括用于执行第一类型的操作的第一间隔和用于执行第二类型的操作的第二间隔的定时周期来操作，其中第一间隔的持续时间大于第二类型的操作的持续时间间隔类型。可以在第二类型的间隔期间对与存储器阵列的至少一部分的温度有关的温度进行采样，并且存储器阵列可以至少部分地基于采样温度来重新配置。第一种类型的操作然后可以在第一种类型的间隔期间在重新配置的存储器阵列上执行。

10. 发明申请

WO2017156028A3 PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE 审中-公开
公开(公告)号：WO2017156028A3
公开(公告)日：2017-09-14
申请号：PCT/US2017/021199
申请日：2017-03-07
申请人： MICRON TECHNOLOGY, INC.
发明人： FACKENTHAL, Richard E.
IPC分类号： G11C11/22
摘要： A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.

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