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1. 发明申请

WO1995001034A1 DIGITAL SIGNAL DEMODULATION METHOD AND DEVICE 审中-公开
标题翻译：数字信号解调方法和设备
公开(公告)号：WO1995001034A1
公开(公告)日：1995-01-05
申请号：PCT/FR1994000724
申请日：1994-06-16
申请人： MATRA COMMUNICATION , ALARD, Michel
发明人： MATRA COMMUNICATION
IPC分类号： H04L27/22
CPC分类号： H04L27/2273 , H04L2027/0057
摘要： A carrier wave phase-modulated signal having 2M states, M being an integer, is demodulated by converting it into a quadrature two-way baseband signal by multiplying it by a local osciallator signal (20) at the translated carrier frequency, and digitising the baseband signal by sampling it at the modulating signal clock frequency. The signal clock is recovered by setting the phase of a bit frequency stabilised local clock (32) and seeking the minimum inter-symbol interference before recovering the carrier.
摘要翻译：通过将具有2M状态（M为整数）的载波相位调制信号通过将其转换成以转换的载波频率的局部奥斯卡拉尔信号（20）转换成正交双向基带信号，并将基带信号通过在调制信号时钟频率进行采样。通过设置位频稳定的本地时钟（32）的相位并在恢复载波之前寻求最小的符号间干扰来恢复信号时钟。

2. 发明申请

WO1997001884A1 PHASE COMPARATOR WITHOUT DEAD ZONE 审中-公开
标题翻译：没有死区的相位比较器
公开(公告)号：WO1997001884A1
公开(公告)日：1997-01-16
申请号：PCT/FR1996000986
申请日：1996-06-24
申请人： MATRA COMMUNICATION , ROBBE, Michel
发明人： MATRA COMMUNICATION
IPC分类号： H03D13/00
CPC分类号： H03D13/004 , H03L7/0891
摘要： A detection logic (10) which is responsive to the phase difference between the two input signals (REFIN, VCOIN) of the comparator provides two detection signals (U, D) to control a charge pump (22) through a control logic (120). The control logic (120) combines the detection signals (U, D) with two pulse signals, one of them (PR) presenting an active impulse of fixed length after each active front of the first input signal (REFIN), the other (PV) presenting an active impulse of fixed length after each active front of the second input signal (VCOIN). For small phase differences, the active impulses of the pulsed signals (PR, PV) present an overlap, and the control logic (120) controls the charge pump (22) as a function of a separation signal (W) which changes status with a fixed delay with respect to the active front of one of DOLLAR he input signals (VCOIN). Thereby, the dead zone of conventional phase comparators due to very short or too short activation of detection signals (U, D) is eliminated.
摘要翻译：响应比较器的两个输入信号（REFIN，VCOIN）之间的相位差的检测逻辑（10）提供两个检测信号（U，D），以通过控制逻辑（120）控制电荷泵（22）。控制逻辑（120）将检测信号（U，D）与两个脉冲信号组合，其中一个（PR）在第一输入信号（REFIN）的每个有效前沿之后呈现固定长度的有效脉冲，另一个（PV））在第二输入信号（VCOIN）的每个有效前沿之后呈现固定长度的有源脉冲。对于小的相位差，脉冲信号（PR，PV）的有效脉冲呈现重叠，并且控制逻辑（120）根据分离信号（W）来控制电荷泵（22），所述分离信号（W）相对于DOLLAR他输入信号（VCOIN）之一的有效前端的固定延迟。因此，由于检测信号（U，D）的激活非常短或太短，常规相位比较器的死区被消除。

3. 发明申请

WO1996013939A1 DIGITAL DATA PACKET MULTIPLEXER, PARTICULARLY FOR DIGITAL TELEVISION 审中-公开
标题翻译：数字数据包多路复用器，特别适用于数字电视
公开(公告)号：WO1996013939A1
公开(公告)日：1996-05-09
申请号：PCT/FR1995001395
申请日：1995-10-23
申请人： MATRA COMMUNICATION , MASSON, Jean-Michel , GRENIER, Frédéric
发明人： MATRA COMMUNICATION
IPC分类号： H04N07/58
CPC分类号： H04N21/434 , H04J3/247 , H04N21/236 , H04N21/242 , H04N21/4302
摘要： A device with a packetising module (C1) including a sensing circuit (22) for sensing synchronisation words in the input stream; a storage unit (23) receiving a series of input stream bytes that have been presented to the sensing circuit (22); means (32) enabling transfer to a packet memory (PM1); and a processor (26) for determining the headers of packets put together from the input stream on the basis of the synchronisation words sensed by the sensing circuit (22), writing the headers into the packet memory (Pmi), and controlling the transfer means (32) so that the length of the header of one packet can be determined while the bytes of a previous packet are being transferred from the storage unit (23) to the packet memory (PM1).
摘要翻译：一种具有分组模块（C1）的设备，包括用于感测所述输入流中的同步字的感测电路（22）存储单元（23），其接收已经呈现给感测电路（22）的一系列输入流字节; （32）能够传送到分组存储器（PM1）; 以及处理器（26），用于基于由感测电路（22）感测的同步字来确定从输入流放置在一起的分组的报头，将报头写入分组存储器（Pmi）中，以及控制传送装置（32），从而可以在先前分组的字节从存储单元（23）传送到分组存储器（PM1）的同时确定一个分组的报头的长度。

4. 发明申请

WO1996021313A1 ACOUSTIC ECHO SUPPRESSOR WITH SUBBAND FILTERING 审中-公开
标题翻译：具有子带过滤功能的声学ECHO抑制器
公开(公告)号：WO1996021313A1
公开(公告)日：1996-07-11
申请号：PCT/FR1995001743
申请日：1995-12-27
申请人： MATRA COMMUNICATION , BOUDY, Jérôme , CAPMAN, François
发明人： MATRA COMMUNICATION
IPC分类号： H04M09/08
CPC分类号： H04M9/082
摘要： The echo suppressor is intended to be placed between a free-hand acoustic interface and a communication network. It comprises a plurality of processing channels mounted in parallel and each affected to one of a plurality of adjacent subbands of the spectral band of the output signal. Each channel comprises an analysis filter which receives the signal, affected with an echo, to be emitted after correction, a second analysis filter receiving the incoming signal, from the network, and supplying an adaptive filter providing an estimated echo in the respective subband at the subtractive input of the subtracter and a synthesis filter. The adaptive filter of at least some of the subbands implements the algorithm RLS with QR breakdown of the incoming signal, in fast processing, with recursive or non-recursive order.
摘要翻译：回波抑制器旨在放置在自由声学接口和通信网络之间。它包括并行安装并且各自影响输出信号的频谱带的多个相邻子带中的一个的多个处理通道。每个通道包括分析滤波器，其接收来自网络的在校正之后发射的受回波影响的信号，接收来自网络的输入信号的第二分析滤波器，并且提供自适应滤波器，该自适应滤波器在相应子带中提供估计回波减法器的减法输入和合成滤波器。至少一些子带的自适应滤波器在快速处理中以递归或非递归顺序实现了输入信号的QR分解的算法RLS。

5. 发明申请

WO1996021218A1 SPEECH CODING METHOD USING SYNTHESIS ANALYSIS 审中-公开
标题翻译：使用合成分析的语音编码方法
公开(公告)号：WO1996021218A1
公开(公告)日：1996-07-11
申请号：PCT/FR1996000004
申请日：1996-01-03
申请人： MATRA COMMUNICATION , NAVARRO, William , MAUC, Michel
发明人： MATRA COMMUNICATION
IPC分类号： G10L09/14
CPC分类号： G10L19/09 , G10L25/93
摘要： A method comprising the steps of performing a linear prediction analysis of a speech signal (S) digitised in a series of frames divided into sub-frames, in order to determine the parameters of a short-term synthesis filter; carrying out an open loop analysis to detect voiced signal frames and determine, for each voiced frame, a degree of signal voicing (MV) and a long-term prediction delay search interval containing a number of delays depending on the degree of voicing; carrying out a closed-loop predictive analysis of the speech signal to select, for at least some sub-frames of the voiced frames, a long-term prediction delay contained in the search interval and constituting a long-term synthesis filter parameter; and determining a stochastic excitation for each sub-frame, to minimise a perceptually weighted deviation between the speech signal and the stochastic excitation filtered by the long-term and short-term synthesis filters.
摘要翻译：一种方法，包括以下步骤：对被划分成子帧的一系列帧中数字化的语音信号（S）执行线性预测分析，以便确定短期合成滤波器的参数; 进行开环分析以检测有声信号帧，并且针对每个有声帧确定包含根据发音程度的多个延迟的信号发声（MV）程度和长期预测延迟搜索间隔; 对所述语音信号进行闭环预测分析，对于所述有声帧的至少一些子帧，选择包含在所述搜索间隔中并构成长期合成滤波器参数的长期预测延迟; 并确定每个子帧的随机激励，以最小化语音信号与由长期和短期合成滤波器滤波的随机激励之间的感知加权偏差。

6. 发明申请

WO1996023384A1 FREQUENCY-DOMAIN ADAPTIVE-FILTER ACOUSTIC ECHO CANCELLER 审中-公开
标题翻译：频域自适应滤波耳塞式收音机
公开(公告)号：WO1996023384A1
公开(公告)日：1996-08-01
申请号：PCT/FR1996000100
申请日：1996-01-22
申请人： MATRA COMMUNICATION , BOUDY, Jérôme , CAPMAN, François
发明人： MATRA COMMUNICATION
IPC分类号： H04M09/08
CPC分类号： H04M9/082
摘要： An echo canceller including an adaptive filter receiving the coefficients of a direct discrete transform in the frequency domain, said coefficients being calculated over a series of blocks in an input signal, and driving, via an inverse transform circuit, the substractive input of an adder for forming an output signal to the network, and a filter coefficient adapting circuit. Said canceller is characterised in that the adapting circuit receives the coefficients of the series of transforms for the output signal sample blocks via a noise reducer. The adapting circuit receives the coefficients of the series of transforms for the output signal sample blocks via a noise reducer.
摘要翻译：一种包括接收频域中的直接离散变换的系数的自适应滤波器的回声消除器，所述系数是通过输入信号中的一系列块来计算的，并且通过逆变换电路驱动用于向网络形成输出信号，以及滤波器系数适配电路。所述消除器的特征在于，适配电路经由降噪器接收输出信号采样块的一系列变换的系数。适应电路经由降噪器接收输出信号采样块的一系列变换的系数。

7. 发明申请

WO1996019081A1 DIGITAL VIDEO PROGRAMME MULTIPLEXING DEVICE 审中-公开
标题翻译：数字视频程序多路复用器件
公开(公告)号：WO1996019081A1
公开(公告)日：1996-06-20
申请号：PCT/FR1995001648
申请日：1995-12-12
申请人： MATRA COMMUNICATION , MASSON, Jean-Michel
发明人： MATRA COMMUNICATION
IPC分类号： H04N07/58
CPC分类号： H04N21/23655 , H04N19/124 , H04N19/14 , H04N19/146 , H04N19/15 , H04N19/172 , H04N19/61
摘要： A device for transmitting a number of video programmes over a transmission channel having a predetermined throughput capacity, including, for each programme channel supplying a multiplexer, a video encoder having a frame-by-frame programmable encoding throughput. The device comprises, on each programme channel, a frame store (20) with a capacity of at least one frame positioned upstream from the programmable encoder (16), and an auxiliary encoder (22) receiving a series of input frames one frame ahead of the the first encoder. Means (26) for comparing the qualities of the frames encoded by the auxiliary encoders with one another or with a reference value control the encoding throughput to balance the output qualities of the various encoders.
摘要翻译：一种用于通过具有预定吞吐量容量的传输信道发送多个视频节目的装置，包括为每个提供复用器的节目频道提供具有逐帧可编程编码吞吐量的视频编码器。该装置在每个节目频道上包括具有位于可编程编码器（16）上游的至少一个帧的容量的帧存储器（20），以及辅助编码器（22），其接收一系列输入帧第一个编码器。用于将由辅助编码器编码的帧的质量彼此相比或用参考值进行比较的装置（26）控制编码吞吐量以平衡各种编码器的输出质量。

8. 发明申请

WO1996019080A1 DIGITAL VIDEO PROGRAMME ENCODING DEVICE 审中-公开
标题翻译：数字视频编程设备
公开(公告)号：WO1996019080A1
公开(公告)日：1996-06-20
申请号：PCT/FR1995001647
申请日：1995-12-12
申请人： MATRA COMMUNICATION , MASSON, Jean-Michel
发明人： MATRA COMMUNICATION
IPC分类号： H04N07/30
CPC分类号： H04N19/154 , H04N19/124 , H04N19/14 , H04N19/146 , H04N19/15 , H04N19/172 , H04N19/61
摘要： A device for encoding an input video stream representing a series of frames by identifying each frame using an information quantity that differs from one frame to the next. The device includes a programmable-throughput video encoder (16), as well as a memory (20) with a capacity of at least one frame positioned upstream from the programmable encoder in the video stream, a second fixed-throughput video encoder (22) receiving the input video stream, and means (26) for comparing the quality of each output image with a reference value and controlling the programmable encoder to maintain quality at a predetermined value.
摘要翻译：一种用于通过使用不同于一帧到下一帧的信息量来识别每个帧来对表示一系列帧的输入视频流进行编码的装置。该设备包括可编程吞吐量视频编码器（16）以及具有位于视频流中的可编程编码器上游的至少一个帧的容量的存储器（20），第二固定吞吐量视频编码器（22）接收输入视频流，以及用于将每个输出图像的质量与参考值进行比较的装置（26），并且控制可编程编码器将质量保持在预定值。

9. 发明申请

WO1996013941A1 DIGITAL DATA PACKET MULTIPLEXER, IN PARTICULAR FOR DIGITAL TELEVISION 审中-公开
标题翻译：数字数据包多路复用器，特别适用于数字电视
公开(公告)号：WO1996013941A1
公开(公告)日：1996-05-09
申请号：PCT/FR1995001397
申请日：1995-10-23
申请人： MATRA COMMUNICATION , MASSON, Jean-Michel , GRENIER, Frédéric
发明人： MATRA COMMUNICATION
IPC分类号： H04N07/58
CPC分类号： H04N21/4347 , H04J3/247 , H04N21/236 , H04N21/2365 , H04N21/434
摘要： A device including a plurality of packetising modules supplying packet memories (PMi) from digital input streams, and multiplexing means (14) for selecting the packet memories from which the multiplex packets are to be retrieved and transferring them sequentially to a device output. Each packet in a packet memory is combined with selection parameters calculated by its packetising module and indicating at least an earliest time, a latest time and preferably an ideal time for transmission of the packet by the multiplexing means. The multiplexing means select the memory from which each multiplex packet is to be retrieved on the basis of the packet transmission time and the respective selection parameters combined with the first packets on stand-by in each of the packet memories.
摘要翻译：一种包括从数字输入流提供分组存储器（PMi）的多个打包模块的装置，以及用于选择要从其中检索多路复用分组并将它们顺序传送到设备输出的分组存储器的多路复用装置（14）。分组存储器中的每个分组与由其打包模块计算的选择参数组合，并且指示至少最早的时间，最近的时间，并且优选地由多路复用装置传输分组的理想时间。多路复用装置根据分组传输时间和与每个分组存储器中的备用的第一分组组合的各个选择参数来选择要从中检索每个复用分组的存储器。

10. 发明申请

WO1996013940A1 DIGITAL DATA PACKET MULTIPLEXER, IN PARTICULAR FOR DIGITAL TELEVISION 审中-公开
标题翻译：数字数据包多路复用器，特别是数字电视
公开(公告)号：WO1996013940A1
公开(公告)日：1996-05-09
申请号：PCT/FR1995001396
申请日：1995-10-23
申请人： MATRA COMMUNICATION , MASSON, Jean-Michel , GRENIER, Frédéric
发明人： MATRA COMMUNICATION
IPC分类号： H04N07/58
CPC分类号： H04J3/247 , H04N21/2365
摘要： A device including a plurality of packetising modules (C1, C2, ..., Cn) supplying packet memories (PM1, PM2, ..., PMm) from digital input streams (IS1, IS2, ..., ISn), and multiplexing means (14). Each packet in a packet memory is combined with selection parameters written into a related parameter memory (ZM1, ZM2, ..., ZMm) by its packetising module. The multiplexing means include processing means connected to the parameter memories via a parameter bus (12) for selecting the packet memories from which the multiplex packets are to be retrieved by analysing the respective selection parameters combined with the first packets on stand-by in each of the packet memories, and transfer means connected to the packet memories via a packet bus (10) and controlled by the processing means to retrieve a series of multiplex packets from the selected packet memories.
摘要翻译：包括从数字输入流（IS1，IS2，...，ISn）提供分组存储器（PM1，PM2，...，PMm）的多个分组化模块（C1，C2，...，Cn）复用装置（14）。分组存储器中的每个分组通过其分组模块与写入相关参数存储器（ZM1，ZM2，...，ZMm）的选择参数组合。多路复用装置包括经由参数总线（12）连接到参数存储器的处理装置，用于通过分析与第一数据包组合的各个选择参数来选择要从其中检索多路复用分组的分组存储器分组存储器和经由分组总线（10）连接到分组存储器并由处理装置控制的传送装置，以从所选择的分组存储器中检索一系列多路复用分组。

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