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    • 2. 发明申请
    • OPTOELECTRONIC FILTER
    • 光电滤波器
    • WO2015017653A1
    • 2015-02-05
    • PCT/US2014/049141
    • 2014-07-31
    • MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    • LOH, WilliamYEGNANARAYANAN, SivaRAM, Rajeev, J.JUODAWLKIS, Paul, William
    • G02F1/035
    • G02F1/2255G02F1/035G02F1/21G02F2001/212
    • An optoelectronic filter having at least one input and an output includes a modulator circuit having at least first and second inputs with a first one of the modulator circuit inputs adapted to couple to a respective one of the at least one input of the optoelectronic filter. The modulator circuit receives at least a first radio frequency (RF) signal having a first power level and a second RF signal having a second, different power level at the first one of the modulator circuit inputs and in response thereto generates a modulated signal at an output thereof. The first RF signal is suppressed relative to the second RF signal in the modulated signal. The optoelectronic filter additionally includes a light source adapted to couple to a second one of the modulator circuit inputs. A corresponding method is also provided.
    • 具有至少一个输入和输出的光电滤波器包括具有至少第一和第二输入的调制器电路,其中第一个调制器电路输入适于耦合到光电滤波器的至少一个输入端中的相应一个输入端。 调制器电路在调制器电路输入的第一个处接收至少具有第一功率电平的第一射频(RF)信号和具有第二不同功率电平的第二RF信号,并响应于此产生调制信号 输出。 第一RF信号相对于调制信号中的第二RF信号被抑制。 光电子滤波器还包括适于耦合到第二调制器电路输入的光源。 还提供了相应的方法。
    • 6. 发明申请
    • SYSTEMS AND METHODS FOR LATCH BASED ANALOG TO DIGITAL CONVERSION
    • 基于LATCH的模拟到数字转换的系统和方法
    • WO2009148458A1
    • 2009-12-10
    • PCT/US2008/066074
    • 2008-06-06
    • LSI CORPORATIONCHMELAR, ErikITO, ChoshuLOH, William
    • CHMELAR, ErikITO, ChoshuLOH, William
    • H03M1/00
    • H03M1/1215H03M1/002H03M1/361
    • Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
    • 本发明的各种实施例提供了用于模数转换的系统和方法。 例如,公开了一种基于锁存器的模数转换器,其包括与一组比较器的第一交错,选择器电路和锁存器。 该组比较器可操作以将模拟输入与相应的参考电压进行比较,并且与时钟相位同步。 选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。 从所选择的输出中导出第一交错输出。 锁存器接收来自第二交错的第二交错输出,并且在时钟相位被断言时是透明的。 选择器输入包括锁存器的输出。
    • 7. 发明申请
    • SYSTEMS AND METHODS FOR SYNCHRONOUS, RETIMED ANALOG TO DIGITAL CONVERSION
    • 用于同步的系统和方法,用于数字转换的模拟
    • WO2009148457A1
    • 2009-12-10
    • PCT/US2008/066060
    • 2008-06-06
    • LSI CORPORATIONITO, ChoshuCHMELAR, ErikLOH, William
    • ITO, ChoshuCHMELAR, ErikLOH, William
    • H03M1/00
    • H03M1/1215H03M1/002H03M1/361
    • The present invention provide systems and methods for analog to digital conversion A retimed analog to digital converter is disclosed that includes a first and second set of sub-level interleaves The first set of sub-level interleaves includes a first sub-level Interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase A global interleave selects one of the first set of comparators based on an output from the second set of sub-level interleaves.
    • 本发明提供用于模数转换的系统和方法公开了一种重新定时的模数转换器,其包括第一和第二组子电平交织。第一组子电平交织包括第一子电平交织,第一子电平交织 与第一时钟相位同步的一组比较器和与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器的第三子电平交织 与第三时钟相位同步的第四子电平交错以及与第四时钟相位同步的第四组比较器的第四子电平交织全局交错基于来自第二组子电平交织的输出选择第一组比较器之一 。