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1. 发明申请

WO2004084266A2 SYSTEM, METHOD AND APPARATUS FOR IMPROVED GLOBAL DUAL-DAMASCENE PLANARIZATION 审中-公开
标题翻译：改进的全球双重平均面积的系统，方法和装置
公开(公告)号：WO2004084266A2
公开(公告)日：2004-09-30
申请号：PCT/US2004/007527
申请日：2004-03-10
申请人： LAM RESEARCH CORPORATION , LOHOKARE, Shrikant, P. , BAILEY, Andrew, D., III , HEMKER, David , COOK, Joel, M.
发明人： LOHOKARE, Shrikant, P. , BAILEY, Andrew, D., III , HEMKER, David , COOK, Joel, M.
IPC分类号： H01L
CPC分类号： H01L21/7684 , H01L21/31116 , H01L21/32115 , H01L21/32135 , H01L21/32136
摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.
摘要翻译：用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。图案化半导体衬底具有填充图案中的多个特征的导电互连材料。导电互连材料具有覆盖层部分。覆盖层部分具有局部不均匀性。去除覆盖层部分的大部分以平坦化上覆层部分。映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

2. 发明申请

WO2004084267A2 SYSTEM, METHOD AND APPARATUS FOR IMPROVED LOCAL DUAL-DAMASCENE PLANARIZATION 审中-公开
标题翻译：用于改进的局部双重平均平面化的系统，方法和装置
公开(公告)号：WO2004084267A2
公开(公告)日：2004-09-30
申请号：PCT/US2004/007530
申请日：2004-03-10
申请人： LAM RESEARCH CORPORATION , LOHOKARE, Shrikant, P. , BAILEY, Andrew, D., III , HEMKER, David , COOK, Joel, M.
发明人： LOHOKARE, Shrikant, P. , BAILEY, Andrew, D., III , HEMKER, David , COOK, Joel, M.
IPC分类号： H01L
CPC分类号： H01L21/32135 , H01L21/32115 , H01L21/32136 , H01L21/7684
摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed an the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.
摘要翻译：用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。图案化半导体衬底具有填充图案中的多个特征的导电互连材料。导电互连材料具有覆盖层部分。覆盖层部分包括局部不均匀性。形成上覆层部分的附加层。附加层和覆盖层部分被平坦化。平坦化工艺基本上完全除去附加层。

3. 发明申请

WO2005061760A1 METHOD AND APPARATUS FOR MATERIAL DEPOSITION 审中-公开
标题翻译：材料沉积的方法和装置
公开(公告)号：WO2005061760A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/040951
申请日：2004-12-07
申请人： LAM RESEARCH CORPORATION
发明人： DORDI, Yezdi , BOYD, John , THIE, William , MARASCHIN, Bob , REDEKER, Fred, C. , COOK, Joel, M.
IPC分类号： C23C18/16
CPC分类号： C23C18/1667 , C23C18/14 , C23C18/1612 , C23C18/1676
摘要： A method and an apparatus are provided for selective heating of a surface of a wafer exposed to an electroless plating solution. Selective heating by a radiant energy source causes a temperature increase at an interface between the wafer surface and the electroless plating solution. This temperature increase causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source. Additionally, a planar member can be positioned over and proximate to the wafer surface to entrap electroless plating solution between the planar member and the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.
摘要翻译：提供了一种方法和装置，用于选择性地加热暴露于化学镀溶液的晶片的表面。通过辐射能源的选择性加热导致晶片表面和化学镀溶液之间的界面处的温度升高。该温度升高导致在晶片表面发生电镀反应。因此，通过化学镀反应将材料沉积在晶片表面上，该电镀反应通过使用适当限定的辐射能源改变晶片表面的温度来启动和控制。此外，平面构件可以位于晶片表面上方并且靠近晶片表面，以在平面构件和晶片表面之间截留化学镀溶液。通过电镀反应沉积的材料形成符合平面构件平坦度的平坦化层。

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