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1. 发明申请

WO2005078629A2 GENETIC ALGORITHMS FOR OPTIMIZATION OF GENOMICS-BASED MEDICAL DIAGNOSTIC TESTS 审中-公开
标题翻译：用于优化基于基因的医学诊断测试的遗传算法
公开(公告)号：WO2005078629A2
公开(公告)日：2005-08-25
申请号：PCT/IB2005/050426
申请日：2005-02-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , SCHAFFER, J., David , SIMPSON, Mark, R.
发明人： SCHAFFER, J., David , SIMPSON, Mark, R.
IPC分类号： G06F19/00
CPC分类号： G06F19/24 , G06F19/20 , G06N3/126
摘要： In a genetic optimization method, the genes of a chromosome population are computationally genetically evolved. The evolving includes evolving a number of expressed genes in each chromosome and employing a fitness criterion evaluated without reference to unexpressed genes of each chromosome. An aptimized chromosome produced by the genetic evolving is selected.
摘要翻译：在遗传优化方法中，染色体群体的基因在计算上是遗传演化的。不断发展的包括在每个染色体中发展出许多表达基因，并采用不参照每个染色体未表达基因的适应度标准。选择由遗传进化产生的适应染色体。

2. 发明申请

WO2008072140A2 RANKING OF FEATURES 审中-公开
标题翻译：功能排名
公开(公告)号：WO2008072140A2
公开(公告)日：2008-06-19
申请号：PCT/IB2007/054939
申请日：2007-12-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , JANEVSKI, Angel, A., J. , SCHAFFER, James, D. , SIMPSON, Mark, R.
发明人： JANEVSKI, Angel, A., J. , SCHAFFER, James, D. , SIMPSON, Mark, R.
IPC分类号： G06N3/12
CPC分类号： G06N3/126
摘要： The invention relates to a method of computing a rank of at least one feature from a pool of features, the method comprising: obtaining (1) a plurality of feature subsets, each feature subset comprising features from the pool of features; and computing (2) the rank of the at least one feature from the pool of features on the basis of an occurrence of the at least one feature in a feature subset. For example, the rank of the at least one feature may be based on the frequency of occurrence of the at least one feature in the plurality of feature subsets. Thus, the method may be advantageously applied to rank features from the pool of features. A new subset of features comprising the top-rank features, which are potentially more useful than a subset of features from the pool of features, may be created from the computed feature ranks values. There may be many other advantageous uses for such a list of ranked features from the pool of features.
摘要翻译：本发明涉及一种从特征池计算至少一个特征的等级的方法，该方法包括：获得（1）多个特征子集，每个特征子集包括来自特征池; 以及基于特征子集中的所述至少一个特征的发生来计算（2）来自所述特征池的所述至少一个特征的秩。例如，至少一个特征的秩可以基于多个特征子集中的至少一个特征的出现频率。因此，该方法可以有利地应用于从特征池中排列特征。可以根据所计算的特征等级值来创建包括顶级特征的新特征子集，其可能比来自特征池的特征子集更有用。对于这样的来自特征池的排名特征列表，可能有许多其他有利用途。

3. 发明申请

WO2009010907A1 DECISION SUPPORT SYSTEM FOR ACUTE DYNAMIC DISEASES 审中-公开
标题翻译：急性动态疾病决策支持系统
公开(公告)号：WO2009010907A1
公开(公告)日：2009-01-22
申请号：PCT/IB2008/052800
申请日：2008-07-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHAFFER, James, D. , SIMPSON, Mark, R. , CHBAT, Nicolas, W. , BANERJEE, Nilanjana , ALSAFADI, Yasser, H.
发明人： SCHAFFER, James, D. , SIMPSON, Mark, R. , CHBAT, Nicolas, W. , BANERJEE, Nilanjana , ALSAFADI, Yasser, H.
IPC分类号： G06F19/00
CPC分类号： G16H50/50 , G06F19/00
摘要： The present invention relates to a medical apparatus (901, 100) for assisting clinicians, nurses or other use.rs in choosing an intervention for the treatment of a patent suffering from an acute dynamic disease, e.g. sepsis. The medical apparatus is based on a method where a model of the disease is adapted or personalised to the patient. To ensure that the apparatus remains capable of predicting the health of the patient, the apparatus is continuously- provided with new patient values and the model is continuously adapted to the new patient values. Since the medical apparatus is configured to be continuously adapted to current state of health, the apparatus is able to assist the user by generating disease management information, e.g. suggestions for medications, to an output device (902, 104).
摘要翻译：本发明涉及一种医疗设备（901,100），用于帮助临床医生，护士或其他使用者选择用于治疗患有急性动态疾病的专利的干预措施，例如，败血症。该医疗装置是基于对患者的疾病模型进行适应或个性化的方法。为了确保该装置能够预测患者的健康状态，该装置被连续地提供新的患者值，并且该模型连续适应于新的患者值。由于医疗装置被配置为连续地适应当前健康状态，因此该装置能够通过产生疾病管理信息来辅助用户，例如，对药物的建议，输出设备（902,104）。

4. 发明申请

WO2003050883A3 SILICON ON INSULATOR DEVICE AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：WO2003050883A3
公开(公告)日：2003-06-19
申请号：PCT/IB2002/004892
申请日：2002-11-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： LETAVIC, Theodore, J. , SIMPSON, Mark, R. , ALBU, Lucian, R. , MUKHERJEE, Satyendranath
IPC分类号： H01L29/78
摘要： A high frequency high voltage Silicon-On-Insulator (SOI) semiconductor device (10) having a shifted doping profile (52) and a method for forming the same are provided. Specifically, the present invention provides a SOI field-effect transistor in which the doping profile is shifted towards the source (22) or body (18) region of the device. The shift in doping profile so that origin (56) thereof is in the body region modifies the channel doping of the device, whereby the channel length is reduced. This allows both transconductance and capacitance to be optimized so that the SOI device can operate at high frequencies. The doping profile is achieved by ion implantation through a mask (60) having openings (64), said mask being shifted towards the body region of the device.

5. 发明申请

WO2003030262A3 SILICON-ON-INSULATOR HIGH VOLTAGE DEVICE STRUCTURE 审中-公开
公开(公告)号：WO2003030262A3
公开(公告)日：2003-04-10
申请号：PCT/IB2002/003737
申请日：2002-09-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： LETAVIC, Theodore, J. , SIMPSON, Mark, R.
IPC分类号： H01L29/786
摘要： A thin layer SOI high-voltage device (100) in which the drift charge is depleted using a three-dimensional MOS capacitor structure (10). The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes (16a, 16b). Each SOI stripe (16a and 16b) is individually circumscribed longitudinally by a dielectric layer (22a, 22b) wherein each dielectric layer (22a, 22b) is longitudinally circumscribed by field platesof a conducting multi-capacitor field plate layer (30) which is electrically shorted to the substrate (12). The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe (16a and 16b) and its encapsulating field plates.

6. 发明申请

WO2003050884A1 DUAL GATE OXIDE HIGH-VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：双栅氧化物高电压半导体器件及其形成方法
公开(公告)号：WO2003050884A1
公开(公告)日：2003-06-19
申请号：PCT/IB2002/004895
申请日：2002-11-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： LETAVIC, Theodore, J. , SIMPSON, Mark, R.
IPC分类号： H01L29/78
CPC分类号： H01L29/7824 , H01L21/28247 , H01L29/42368
摘要： A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.
摘要翻译：提供一种双栅极氧化物高压半导体器件及其制造方法。具体地，根据本发明形成的器件包括半导体衬底，在衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的硅层和形成在硅层上的顶部氧化物层。邻近顶部氧化物层的边缘，形成双栅氧化物。双栅极氧化物允许优化器件的导通电阻和击穿电压。

7. 发明申请

WO2002069408A2 SOI LDMOS STRUCTURE WITH IMPROVED SWITCHING CHARACTERISTICS 审中-公开
标题翻译： SOI LDMOS结构具有改进的开关特性
公开(公告)号：WO2002069408A2
公开(公告)日：2002-09-06
申请号：PCT/IB2002/000411
申请日：2002-02-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： PETRUZZELLO, John , LETAVIC, Theodore, J. , SIMPSON, Mark, R.
IPC分类号： H01L29/78
CPC分类号： H01L29/402 , H01L29/0847 , H01L29/0852 , H01L29/41758 , H01L29/42368 , H01L29/7394 , H01L29/7824
摘要： An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.
摘要翻译：提出了具有横向漂移区域（32）和导电顶部场板（44,44a）的诸如Loi-LDMOS或Soi-LIGBT的绝缘体上硅晶体管器件的方法和结构。该方法包括通过减少连接到栅电极（36,36a）的压板（44,44a）的部分来减小栅极与漏极电容（301,401），从而降低栅电极栅极（36,36a）与漂移区域（32）和漏极（34）连接。这导致在切换晶体管时能量消耗降低，并且操作更有效。在较高的漏极电压下，栅极到漏极电容（301,401）的降低速率甚至更快，从而在高电压应用中显着提高了能量效率。

8. 发明申请

WO2003050883A2 HIGH FREQUENCY HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE WITH MASK VARIABLE INVERSION CHANNEL AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：具有屏蔽变频反相信道的高频高压绝缘子器件及其形成方法
公开(公告)号：WO2003050883A2
公开(公告)日：2003-06-19
申请号：PCT/IB2002/004892
申请日：2002-11-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： LETAVIC, Theodore, J. , SIMPSON, Mark, R. , ALBU, Lucian, R. , MUKHERJEE, Satyendranath
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/266 , H01L29/0847 , H01L29/36 , H01L29/66674 , H01L29/7394 , H01L29/7824
摘要： A high frequency high voltage semiconductor device having a shifted doping profile and method for forming the same are provided. Specifically, the present invention provides a semiconductor device (
摘要翻译：提供具有偏移掺杂分布的高频高压半导体器件及其形成方法。具体而言，本发明提供一种半导体器件（<250V），其中掺杂分布向器件的源极或体区移动。根据本发明的掺杂分布的偏移允许跨导和电容被优化，使得SOI器件可以在高频下工作。

9. 发明申请

WO2003003464A3 HV-SOI LDMOS DEVICE WITH INTEGRATED DIODE TO IMPROVE RELIABILITY AND AVALANCHE RUGGEDNESS 审中-公开
公开(公告)号：WO2003003464A3
公开(公告)日：2003-01-09
申请号：PCT/IB2002/002414
申请日：2002-06-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： PETRUZZELLO, John , LETAVIC, Theodore, J. , SIMPSON, Mark, R.
IPC分类号： H01L27/02
摘要： A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.

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