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1. 发明申请

WO2006129210A2 IMPROVED DIVERSITY ANTENNA ASSEMBLY FOR WIRELESS COMMUNICATION EQUIPMENT 审中-公开
标题翻译：改善无线通信设备的多样性天线装配
公开(公告)号：WO2006129210A2
公开(公告)日：2006-12-07
申请号：PCT/IB2006051527
申请日：2006-05-16
申请人： KONINKL PHILIPS ELECTRONICS NV , RAMBEAU VINCENT , VAN SINDEREN JAN , BREKELMANS JOHANNES H A , NOTTEN MARC G M
发明人： RAMBEAU VINCENT , VAN SINDEREN JAN , BREKELMANS JOHANNES H A , NOTTEN MARC G M
IPC分类号： H01Q7/00 , H01Q9/42
CPC分类号： H01Q7/00
摘要： An antenna assembly (AA), forwireless communication equipment, comprises i) an antenna structure comprising at least a loop type antenna (LA) arranged to deliver a first current when it is used in a balanced mode and/or a second current when it is used in an unbalanced mode with respect to a ground plane (GP) from received radio signals, and Ë) current extraction means (Al) coupled to the antenna structure (LA) and arranged to be placed in at least a first state in which they deliver the first or second current and a second state in which they simultaneously deliver the first and second currents either separately or mixed together.
摘要翻译：一种用于无线通信设备的天线组件（AA），包括：i）天线结构，其包括至少一个环形天线（LA），该环形天线布置成当平衡模式下使用时传送第一电流，并且当它是以相对于接收的无线电信号的接地平面（GP）的不平衡模式使用，以及Ë）耦合到天线结构（LA）的电流提取装置（A1），并布置成至少置于第一状态传送第一或第二电流和第二状态，其中它们分别或混合在一起，同时传送第一和第二电流。

2. 发明申请

WO02093732A3 TUNER CIRCUIT USING POLYPHASE FILTERS AND MIXER 审中-公开
标题翻译：使用多相滤波器和混频器的调谐电路
公开(公告)号：WO02093732A3
公开(公告)日：2003-09-25
申请号：PCT/IB0201625
申请日：2002-05-08
申请人： KONINKL PHILIPS ELECTRONICS NV , STIKVOORT EDUARD F , VAN SINDEREN JAN , RUITENBURG LEONARDUS , KUEHN ARIE , GIELIS GERARDUS C M , NOTTEN MARC G M , TOMBEUR ANTOON M H , JEURISSEN GERARDUS M D
发明人： STIKVOORT EDUARD F , VAN SINDEREN JAN , RUITENBURG LEONARDUS , KUEHN ARIE , GIELIS GERARDUS C M , NOTTEN MARC G M , TOMBEUR ANTOON M H , JEURISSEN GERARDUS M D
IPC分类号： H04N5/44 , H03D3/00 , H03D7/16 , H03J3/08 , H04B1/26
CPC分类号： H03D7/166 , H03D3/007 , H03D7/163 , H03J3/08
摘要： The invention relates to an integrated tuner circuit, preferably to a TV-tuner circuit using double conversion. It is a major purpose of the invention to modify a prior art tuner circuit in a way such that a high degree of integration is achieved. This is contrary to the state of the art in which tuners comprise many discrete components and comprise a lot of adjusting and alignment points. A high degree of integration will substantially reduce the costs, not only production costs but also costs accompanying the complex adjusting procedure. Also, by increasing the degree of integration dimensions may be substantially reduced. In view of the above purpose the invention provides an integrated tuner circuit having a first polyphase filter (10) at the input side of a fully complex mixer (13), and a second polyphase filter (15) at the output of the fully complex mixer (13).
摘要翻译：本发明涉及一种集成调谐器电路，优选地涉及一种使用双转换的电视调谐器电路。本发明的主要目的是以实现高度集成的方式修改现有技术的调谐器电路。这与现有技术的现有技术相反，其中调谐器包括许多分立元件并且包括大量的调节和对准点。高度整合将大大降低成本，不仅生产成本，而且伴随复杂调整程序的成本。此外，通过增加集成度的程度可以显着降低。鉴于上述目的，本发明提供了一种在全复合混合器（13）的输入侧具有第一多相滤波器（10）的集成调谐器电路，以及在全复合混频器的输出端处的第二多相滤波器（15）（13）。

3. 发明申请

WO2009019633A2 HARMONIC REJECTION MIXER UNIT AND METHOD FOR PERFORMING A HARMONIC REJECTION MIXING 审中-公开
标题翻译：谐波抑制混合器单元和执行谐波抑制混合的方法
公开(公告)号：WO2009019633A2
公开(公告)日：2009-02-12
申请号：PCT/IB2008053057
申请日：2008-07-30
申请人： NXP BV , VAN SINDEREN JAN , AMIOT SEBASTIEN , HESEN LEONARDUS H M , BREKELMANS JOHANNES H A
发明人： VAN SINDEREN JAN , AMIOT SEBASTIEN , HESEN LEONARDUS H M , BREKELMANS JOHANNES H A
IPC分类号： H03D7/14 , H03D7/18
CPC分类号： H03D7/1441 , H03D7/145 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/165 , H03D7/166 , H03D7/18 , H03D2200/0086
摘要： A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of
摘要翻译：提供了一种谐波抑制混频器单元，其包括输入（RF），至少一个具有至少两个晶体管单元（T3a，T3b; T4a，T4b）的谐波抑制单元（HRU），用于将来自输入（RF）具有乘法信号（ELO）。谐波抑制混频器单元还包括晶体管控制信号生成单元（GGU），用于产生用于至少一个谐波抑制单元的至少两个晶体管单元（T3a，T3b; T4a，T4b）的晶体管控制信号（GS1-GS4）（HR1）通过从本地振荡器信号（LO）导出晶体管控制信号（GS1-GS4）。以占空比<50％生成用于至少两个晶体管单元（T3a，T3b; T4a，T4b）的晶体管控制信号（GS3，GS4），并产生使得乘法信号ELO的形状得以实现通过来自晶体管单元（T3a，T3b; T4a，T4b）的输出信号的构造求和。产生晶体管控制信号（GS1-GS4），使得只执行来自具有相同符号或零的晶体管单元的输出信号的总和。

4. 发明申请

WO2009057051A3 PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混频器
公开(公告)号：WO2009057051A3
公开(公告)日：2010-04-15
申请号：PCT/IB2008054466
申请日：2008-10-29
申请人： NXP BV , BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
发明人： BREKELMANS JOHANNES H A , DE JONG GERBEN W , EL WAFFAOUI RACHID , JEURISSEN DENNIS , VAN SINDEREN JAN , LEE SIMON WK
IPC分类号： H03D7/16 , H03D7/18
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译：一种包括无源谐波抑制混频器的电子设备。无源谐波抑制混频器具有连接到几个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。

5. 发明申请

WO2009060337A3 MIXER ARCHITECTURE 审中-公开
标题翻译：混合体系结构
公开(公告)号：WO2009060337A3
公开(公告)日：2010-01-21
申请号：PCT/IB2008054444
申请日：2008-10-28
申请人： NXP BV , HESEN LEONARDUS H M , VAN SINDEREN JAN
发明人： HESEN LEONARDUS H M , VAN SINDEREN JAN
IPC分类号： H03D7/16
CPC分类号： H03D7/165
摘要： This invention relates to a device, a method, a system, wherein at least two mixer units are associated with at least two different mixer frequencies, and wherein each of said mixer units comprises a first input configured to receive at least one input signal to be mixed, and wherein at least one amplifier is coupled to said at least two mixer units, wherein each of said at least one amplifier is coupled to at least two outputs of at least two different mixer units ofsaid at least two mixer units.
摘要翻译：本发明涉及一种设备，方法，系统，其中至少两个混频器单元与至少两个不同的混频器频率相关联，并且其中每个所述混频器单元包括被配置为接收至少一个输入信号的第一输入混合，并且其中至少一个放大器耦合到所述至少两个混频器单元，其中所述至少一个放大器中的每一个耦合到至少两个混合器单元的至少两个不同的混合器单元的至少两个输出端，所述混频器单元至少包括两个混频器单元。

6. 发明申请

WO2009113000A2 OUTPUT STAGE FOR A DIGITAL RF TRANSMITTER, METHOD FOR PROVIDING AN RF OUTPUT SIGNAL IN A DIGITAL RF TRANSMITTER, AND DIGITAL RF TRANSMITTER 审中-公开
标题翻译：用于数字RF发射机的输出级，用于在数字RF发射机中提供RF输出信号的方法和数字RF发射机
公开(公告)号：WO2009113000A2
公开(公告)日：2009-09-17
申请号：PCT/IB2009050960
申请日：2009-03-09
申请人： NXP BV , HE XIN , COLLADOS ASENSIO MANEL , PAVLOVIC NENAD , VAN SINDEREN JAN
发明人： HE XIN , COLLADOS ASENSIO MANEL , PAVLOVIC NENAD , VAN SINDEREN JAN
IPC分类号： H04B1/04
CPC分类号： H04B1/0483
摘要： An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.
摘要翻译：提供了一种用于数字RF发射器的输出级（1）。输出级包括：适于接收要发送的输入信号（RFin，b7-b0）的输入; 多个N个功率放大部分（S1，S2，S3，S4）; 以及提供输出电压信号的输出（A，B）。 N个功率放大部分（S1，S2，S3，S4）中的每一个被布置成接收输入信号（RFin，b7-b0），并且包括适于提供相应输出信号的变压器（T1，T2，T3，T4）。每个变压器包括初级和次级级; N个功率放大部（S1，S2，S3，S4）的变压器（T1，T2，T3，T4）的次级组合，从而提供输出级的组合输出电压信号。 N个功率放大部分（S1，S2，S3，S4）被适配成使得输入信号（RFin，b7-b0）被包括不同相位的时钟信号（clock1，clock2，clock3，clock4）锁存。

7. 发明申请

WO2010125506A3 CALIBRATION OF PASSIVE HARMONIC-REJECTION MIXER 审中-公开
标题翻译：被动谐波抑制混合器的校准
公开(公告)号：WO2010125506A3
公开(公告)日：2011-07-21
申请号：PCT/IB2010051784
申请日：2010-04-23
申请人： NXP BV , JEURISSEN DENNIS , DE JONG GERBEN WILLEM , VAN SINDEREN JAN , BREKELMANS JOHANNES HUBERTUS ANTONIUS
发明人： JEURISSEN DENNIS , DE JONG GERBEN WILLEM , VAN SINDEREN JAN , BREKELMANS JOHANNES HUBERTUS ANTONIUS
IPC分类号： H03D7/14
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译：一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4）的加权模块以使输出信号匹配期望的输出信号。

8. 发明申请

WO2009121861A3 RADIO FREQUENCY MODULATOR 审中-公开
标题翻译：无线电频率调制器
公开(公告)号：WO2009121861A3
公开(公告)日：2010-07-08
申请号：PCT/EP2009053782
申请日：2009-03-31
申请人： NXP BV , HE XIN , VAN SINDEREN JAN , COLLADOS ASENSIO MANEL , PAVLOVIC NENAD
发明人： HE XIN , VAN SINDEREN JAN , COLLADOS ASENSIO MANEL , PAVLOVIC NENAD
IPC分类号： H03D7/14 , H03G1/00 , H03G3/30
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/165 , H03D2200/0019 , H03D2200/0084 , H03D2200/009 , H03G1/0088
摘要： The present application relates to a radio frequency modulator comprising at least two unit cells, wherein at least one unit cell comprises a local oscillator input terminal. The at least one unit cell is configured to generate at least one up-converted output signal depending on a local oscillator signal. The at least one unit cell comprises at least one data input terminal, wherein the data input terminal is arranged to receive at least a first data signal. The at least one unit cell is configured such that the generating of the up-converted output signal is deactivatable at least depending on the first data signal. The present application relates also to a transmitter, a method for generating an up-converted output signal and a computer readable medium having a computer program stored thereon.
摘要翻译：本申请涉及一种包括至少两个单元的射频调制器，其中至少一个单元包括本地振荡器输入端。所述至少一个单元单元被配置为根据本地振荡器信号产生至少一个上变频输出信号。所述至少一个单元单元包括至少一个数据输入端，其中所述数据输入端被布置为接收至少第一数据信号。至少一个单元单元被配置为使得上变频输出信号的产生至少取决于第一数据信号而失活。本申请还涉及发射机，用于产生上变频输出信号的方法和其上存储有计算机程序的计算机可读介质。

9. 发明申请

WO2007023417A3 MULTI-TUNER APPARATUS FOR RECEIVING RF SIGNALS 审中-公开
标题翻译：用于接收射频信号的多功能设备
公开(公告)号：WO2007023417A3
公开(公告)日：2007-06-07
申请号：PCT/IB2006052811
申请日：2006-08-15
申请人： NXP BV , VAN SINDEREN JAN , SENESCHAL FRANCOIS , POTIER JACQUES
发明人： VAN SINDEREN JAN , SENESCHAL FRANCOIS , POTIER JACQUES
IPC分类号： H04N5/50
CPC分类号： H04B1/18 , H03J1/0083
摘要： A multi-tuner apparatus comprises a splitter (S) for received RF signals. The splitter has a splitter output (U) for connection to a plurality of tuners. To reduce signal degradation and dissipation the output impedance of the splitter output is substantially lower than the input impedance of each of the tuners.
摘要翻译：多调谐器装置包括用于接收的RF信号的分路器（S）。分路器具有用于连接到多个调谐器的分路器输出（U）。为了降低信号衰减和耗散，分路器输出的输出阻抗基本上低于每个调谐器的输入阻抗。

10. 发明申请

WO0205423A2 AGC CIRCUIT 审中-公开
标题翻译： AGC电路
公开(公告)号：WO0205423A2
公开(公告)日：2002-01-17
申请号：PCT/EP0107401
申请日：2001-06-28
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： VAN SINDEREN JAN
IPC分类号： H03G3/20 , H03G3/00 , H03G3/30 , H04B1/16
CPC分类号： H03G3/001 , H03G3/3036
摘要： AGC circuit comprising a digitally controlled amplifier being provided with a gain control loop including a level detector, a threshold circuit and a digital gain control signal generator being coupled to a gain control input of the digitally controlled amplifier for supplying thereto a digital gain control signal. To prevent astable gain settings of the digitally controlled amplifier from occurring a continuously controlled amplifier is being coupled between an output of the digitally controlled amplifier and the level detector, an output of the level detector being coupled to a gain control input of the continuously controlled amplifier for supplying thereto an continuous gain control signal, the gain variation range of the continuously controlled amplifier at least corresponding to the gain step variation of the digitally controlled amplifier at an incremental step of said digital gain control signal.
摘要翻译：包括数字控制放大器的AGC电路配备有包括电平检测器，阈值电路和数字增益控制信号发生器的增益控制环路，该数字增益控制信号发生器连接到数字控制放大器的增益控制输入端，用于向其提供数字增益控制信号。为了防止数字控制放大器发生不稳定的增益设置，连续控制的放大器连接在数字控制放大器的输出端和电平检测器之间，电平检测器的输出端连接到连续控制的放大器的增益控制输入端用于向其提供连续增益控制信号，所述连续控制放大器的增益变化范围至少对应于所述数字增益控制信号的增量步长处的数字控制放大器的增益阶跃变化。

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