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1. 发明申请

WO2019064111A1 RESISTIVE MEMORY DEVICE 审中-公开
公开(公告)号：WO2019064111A1
公开(公告)日：2019-04-04
申请号：PCT/IB2018/056992
申请日：2018-09-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE (RWTH) AACHEN , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： KOELMANS, Wabe , SEBASTIAN, Abu , JONNALAGADDA, Vara , SALINGA, Martin , KERSTING, Benedikt
IPC分类号： G11C11/56
摘要： The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal. The phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers. Additional implementations of the resistive memory device include a related method, a related control unit, a related memory cell and a related computer program product.

2. 发明申请

WO2021044251A1 ELASTIC-CENTROID BASED CLUSTERING 审中-公开
公开(公告)号：WO2021044251A1
公开(公告)日：2021-03-11
申请号：PCT/IB2020/057928
申请日：2020-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： MORAITIS, Timoleon , SEBASTIAN, Abu
IPC分类号： G06F17/00
摘要： A computer device, a non-transitory computer storage medium, and a computer-implemented method of pattern recognition utilizing an elastic clustering algorithm. A sequence of input datapoints are assigned to a particular cluster of K clusters based on a distance from a centroid k representing a center of the particular cluster. The centroid k in each of the K clusters is shifted from a first position to a second position closer than the first position from the sequence of input datapoints. A location of the centroid k in each of the K clusters is relaxed from the second position toward an equilibrium point in the particular cluster of the K clusters. The relaxing of the location of the centroid k occurs according to an elasticity pull factor based on a distance between the centroid k of the particular cluster at a time t.

3. 发明申请

WO2021044242A1 PERFORMING DOT PRODUCT OPERATIONS USING A MEMRISTIVE CROSSBAR ARRAY 审中-公开
公开(公告)号：WO2021044242A1
公开(公告)日：2021-03-11
申请号：PCT/IB2020/057684
申请日：2020-08-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： DAZZI, Martino , FRANCESE, Pier Andrea , SEBASTIAN, Abu , LE GALLO-BOURDEAU, Manuel , ELEFTHERIOU, Evangelos Stavros
IPC分类号： G06N3/04
摘要： A method, computer system, and computer program product of performing a matrix convolution on a multidimensional input matrix for obtaining a multidimensional output matrix. The matrix convolution may include a set of dot product operations for obtaining all elements of the output matrix. Each dot product operation of the set of dot product operations may include an input submatrix of the input matrix and at least one convolution matrix. The method may include providing a memristive crossbar array configured to perform a vector matrix multiplication. A subset of the set of dot product operations may be computed by storing the convolution matrices of the subset of dot product operations in the crossbar array and inputting to the crossbar array one input vector comprising all distinct elements of the input submatrices of the subset.

4. 发明申请

WO2020049492A1 PROBABILITY PROPAGATION OVER FACTOR GRAPHS 审中-公开
公开(公告)号：WO2020049492A1
公开(公告)日：2020-03-12
申请号：PCT/IB2019/057472
申请日：2019-09-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM DEUTSCHLAND GMBH
发明人： CHERUBINI, Giovanni , MORAITIS, Timoleon , SEBASTIAN, Abu
IPC分类号： G06N3/06
摘要： Methods and apparatus are provided for implementing propagation of probability distributions of random variables over a factor graph. Such a method includes providing a spiking neural network, having variable nodes interconnected with factor nodes, corresponding to the factor graph. Each of the nodes comprises a set of neurons configured to implement computational functionality of that node. The method further comprises generating, for each of a set of the random variables, at least one spike signal in which the probability of a possible value of that variable is encoded via the occurrence of spikes in the spike signal, and supplying the spike signals for the set of random variables as inputs to the neural network at respective variable nodes. The probability distributions are propagated via the occurrence of spikes in signals propagated through the neural network.

5. 发明申请

WO2022101725A1 MULTI-TERMINAL NEUROMORPHIC DEVICE 审中-公开
公开(公告)号：WO2022101725A1
公开(公告)日：2022-05-19
申请号：PCT/IB2021/059858
申请日：2021-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
发明人： SYED, Ghazi Sarwat , SEBASTIAN, Abu , MORAITIS, Timoleon , KERSTING, Benedikt
IPC分类号： G06N3/063
摘要： A neuromorphic memory element (100,200,300,706) comprises a memristor, a plurality of the neuromrophic memory elements (100,200,300,706) and a method for operating the same may be provided. The memristor comprises an input signal terminal (104), an output signal terminal (106), and a control signal terminal, and a memristive active channel (108) comprising a phase change material. The memristive active channel (108) extends longitudinal between the input signal terminal (104) and the output signal terminal (106), and a control signal voltage at the control signal terminal is configured to represent volatile biological neural processes of the neuromorphic memory element (100,200,300,706), and a bias voltage between the input signal terminal (104) and the output terminal (106) is configured to represent non-volatile biological processes of the neuromorphic memory element (100,200,300,706).

6. 发明申请

WO2016067139A1 NEUROMORPHIC SYNAPSES 审中-公开
标题翻译：神经突触
公开(公告)号：WO2016067139A1
公开(公告)日：2016-05-06
申请号：PCT/IB2015/057824
申请日：2015-10-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM RESEARCH GMBH
发明人： ELEFTHERIOU, Evangelos Stavros , PANTAZI, Angeliki , SEBASTIAN, Abu , TUMA, Tomas
IPC分类号： G06N3/10
CPC分类号： G06N3/049 , G06N3/063 , G06N3/088
摘要： A neuromorphic synapse (11) comprises a resistive memory cell (15) connected in circuitry having first and second input terminals (21,22).These input terminals (21,22) respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry also has an output terminal (23) for providing a synaptic output signal which is dependent on resistance of the memory cell (15).The circuitry is operable such that the synaptic output signal is provided at the output terminal (23) in response to application at the first input terminal (21) of the read portion of the pre-neuron action signal,and such that a programming signal,for programming resistance of the memory cell (15), is applied to the cell (15) in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals (21,22) respectively. The synapse (11) can be adapted for operation with identical pre-neuron and post-neuron action signals.
摘要翻译：神经突触（11）包括在具有第一和第二输入端子（21,22）的电路中连接的电阻性存储单元（15）。这些输入端子（21,22）分别接收预神经元和神经元后神经元动作信号，每个具有读取部分和写入部分。电路还具有用于提供取决于存储器单元（15）的电阻的突触输出信号的输出端子（23）。该电路可操作使得突触输出信号在输出端（23）处被响应地提供以应用于前神经元动作信号的读取部分的第一输入端（21），并且使得用于编程存储单元（15）的电阻的编程信号作为响应应用于单元（15）分别在第一和第二输入端子（21,22）处同时应用神经元前神经元和后神经元作用信号的写入部分。突触（11）可以适应于具有相同的前神经元和神经元后动作信号的操作。

7. 发明申请

WO2022229727A1 MEMORY MAPPING OF ACTIVATIONS FOR CONVOLUTIONAL NEURAL NETWORK EXECUTIONS 审中-公开
公开(公告)号：WO2022229727A1
公开(公告)日：2022-11-03
申请号：PCT/IB2022/052592
申请日：2022-03-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
发明人： DAZZI, Martino , FRANCESE, Pier Andrea , SEBASTIAN, Abu , ELEFTHERIOU, Evangelos Stavros
IPC分类号： G06N3/08 , G06T1/60
摘要： A memory controller circuit for mapping data of a convolutional neural network to a physical memory is disclosed. The memory controller circuit comprises a receiving unit to receive a selection parameter value, and a mapping unit to map pixel values of one layer of the convolutional neural network to memory words of the physical memory according to one of a plurality of mapping schemas, wherein the mapping is dependent on the value of the received selection parameter value.

8. 发明申请

WO2022189872A1 RESISTIVE MEMORY DEVICE FOR MATRIX-VECTOR MULTIPLICATIONS 审中-公开
公开(公告)号：WO2022189872A1
公开(公告)日：2022-09-15
申请号：PCT/IB2022/051322
申请日：2022-02-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM ISRAEL SCIENCE AND TECHNOLOGY LTD. , IBM (CHINA) INVESTMENT COMPANY LTD.
发明人： KHADDAM-ALJAMEH, Riduan , LE GALLO-BOURDEAU, Manuel , SEBASTIAN, Abu
IPC分类号： G06F17/16
摘要： A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.

9. 发明申请

WO2012120400A1 PROGRAMMING OF PHASE-CHANGE MEMORY CELLS 审中-公开
标题翻译：相变记忆细胞的编程
公开(公告)号：WO2012120400A1
公开(公告)日：2012-09-13
申请号：PCT/IB2012/050846
申请日：2012-02-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu , FREY, Urs
发明人： PANTAZI, Angeliki , PAPANDREOU, Nikolaos , POZIDIS, Charalampos , SEBASTIAN, Abu , FREY, Urs
IPC分类号： G11C16/10
CPC分类号： G11C11/5678 , G11C7/1006 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： Methods and apparatus are provided for programming a phase-change memory cell (10). A bias voltage signal (V BL ) is applied to the cell. A measurement portion (m) of this bias voltage signal has a profile which varies with time. A measurement (T M ), which is dependent on a predetermined condition being satisfied, is then made. The predetermined condition is dependent on cell current during the measurement portion (m) of the bias voltage signal. A programming signal is generated in dependence on the measurement (T M ), and the programming signal is applied to program the cell (10).
摘要翻译：提供了用于编程相变存储器单元（10）的方法和装置。偏置电压信号（VBL）被施加到单元。该偏置电压信号的测量部分（m）具有随时间变化的轮廓。然后进行取决于满足预定条件的测量（TM）。预定条件取决于偏置电压信号的测量部分（m）期间的电池电流。根据测量（TM）产生编程信号，并且应用编程信号对单元（10）进行编程。

10. 发明申请

WO2022101741A1 DRIFT AND NOISE CORRECTED MEMRISTIVE DEVICE 审中-公开
公开(公告)号：WO2022101741A1
公开(公告)日：2022-05-19
申请号：PCT/IB2021/060194
申请日：2021-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM (CHINA) INVESTMENT COMPANY LTD. , IBM ISRAEL - SCIENCE & TECHNOLOGY LTD.
发明人： SYED, Ghazi Sarwat , KERSTING, Benedikt , SEBASTIAN, Abu
IPC分类号： G01C13/00
摘要： A memristor memory device(100) comprises a memristive memory cell(102), an input terminal(104), an output terminal(108), and a gate terminal(112). The input terminal(104) and the output terminal(108) are directly attached to the memristive memory cell(102), and the gate terminal(112) is electrically isolated from the memristive memory cell(102). The gate terminal(112) is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell(102), by which a correction of non-ideal conductance modulations of the memristor memory device(100) is achieved.

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