专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013101023A1 REDUCING THE NUMBER OF SCALING ENGINES USED IN A DISPLAY CONTROLLER TO DISPLAY A PLURALITY OF IMAGES ON A SCREEN 审中-公开
标题翻译：减少在显示控制器中使用的缩放引擎数量，以在屏幕上显示大量图像
公开(公告)号：WO2013101023A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067728
申请日：2011-12-29
申请人： INTEL CORPORATION , ZHANG, Wujian , KURUPATI, Sreenath
发明人： ZHANG, Wujian , KURUPATI, Sreenath
IPC分类号： G09G5/36
CPC分类号： G09G5/397 , G06T3/40 , G09G5/363 , G09G2340/0407 , G09G2340/10 , G09G2340/12 , G09G2352/00 , G09G2360/06 , G09G2370/20 , H04N5/46 , H04N21/41407 , H04N21/42653 , H04N21/431 , H04N21/440263
摘要： Methods and apparatuses to reduce the number of scaling engines used in a display controller that displays image content associated with a plurality of image sources on a screen are provided. A first multiplexer may receive image content from a plurality of storage devices, and select first image content from one of the plurality of image sources. A first scaling engine may process the selected first image content, wherein a plurality of multiplexers can receives an output of the first scaling engine and the image content from the plurality of storage devices, respectively. Each one of the plurality of multiplexers may output either the image content input to the multiplexer or the output of the first scaling engine depending on which image content was scaled by the first scaling engine. Additionally, a plurality of post-processors may perform additional post-processing on the output of the plurality of multiplexer, respectively.
摘要翻译：提供了减少在显示控制器中使用的缩放引擎的数量的方法和装置，其显示与屏幕上的多个图像源相关联的图像内容。第一多路复用器可以从多个存储设备接收图像内容，并从多个图像源之一中选择第一图像内容。第一缩放引擎可以处理所选择的第一图像内容，其中多个多路复用器可以分别从多个存储设备接收第一缩放引擎的输出和图像内容。多个多路复用器中的每一个可以根据由第一缩放引擎缩放的图像内容输出输入到多路复用器的图像内容或第一缩放引擎的输出。另外，多个后处理器可以分别在多个多路复用器的输出上执行附加的后处理。

2. 发明申请

WO2013095460A1 PERCEPTUAL LOSSLESS COMPRESSION OF IMAGE DATA TO REDUCE MEMORY BANDWIDTH AND STORAGE 审中-公开
标题翻译：图像数据的无损无损压缩减少记忆带宽和存储
公开(公告)号：WO2013095460A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066590
申请日：2011-12-21
申请人： INTEL CORPORATION , KURUPATI, Sreenath , RAO, Tanuja , GUPTA, Arup
发明人： KURUPATI, Sreenath , RAO, Tanuja , GUPTA, Arup
IPC分类号： H04N5/91 , H04N7/26 , H03M7/30
CPC分类号： H04N19/503 , H03M7/3059 , H03M7/3075 , H04N9/8042 , H04N19/124 , H04N19/182 , H04N19/593
摘要： Methods and systems may include a compression module having logic to receive a pixel difference signal associated with an image, and conduct a compression of the pixel difference signal based on a value of the pixel difference signal. The logic can also generate a modified pixel difference signal based on the compression, wherein the compression may enable the image to be stored to dynamic random access memory (DRAM) in a compressed state.
摘要翻译：方法和系统可以包括具有接收与图像相关联的像素差异信号的逻辑的压缩模块，并且基于像素差信号的值来进行像素差分信号的压缩。该逻辑还可以基于压缩产生经修改的像素差异信号，其中压缩可以使图像能够以压缩状态存储到动态随机存取存储器（DRAM）。

3. 发明申请

WO2006050290A2 TRANSFERRING A VIDEO FRAME FROM MEMORY INTO AN ON-CHIP BUFFER FOR VIDEO PROCESSING 审中-公开
标题翻译：将视频帧从内存传输到片上缓冲器以进行视频处理
公开(公告)号：WO2006050290A2
公开(公告)日：2006-05-11
申请号：PCT/US2005/039325
申请日：2005-10-27
申请人： INTEL CORPORATION , NICKERSON, Brian , WONG, Samuel , CHAUDHURI, Santanu , LIU, Jonathan , KURUPATI, Sreenath
发明人： NICKERSON, Brian , WONG, Samuel , CHAUDHURI, Santanu , LIU, Jonathan , KURUPATI, Sreenath
IPC分类号： H04N7/01
CPC分类号： H04N7/0125 , G09G5/391 , G09G5/395 , G09G2340/0407 , H04N7/0135
摘要： A portion of a video frame is transferred via a memory burst transfer, from memory to an on-chip buffer. The on-chip buffer has a width that is the same as the memory burst width for the memory. Video processing is performed upon the transferred portion. Other embodiments are also described and claimed.
摘要翻译：视频帧的一部分通过存储器突发传输从存储器传输到片上缓冲器。片上缓冲器的宽度与内存的内存突发宽度相同。视频处理在被传送的部分上执行。其他实施例也被描述和要求保护。

4. 发明申请

WO2006036571A1 AN APPARATUS AND METHOD FOR EDGE HANDLING IN IMAGE PROCESSING 审中-公开
标题翻译：图像处理边缘处理的装置和方法
公开(公告)号：WO2006036571A1
公开(公告)日：2006-04-06
申请号：PCT/US2005/032932
申请日：2005-09-13
申请人： INTEL CORPORATION , KURUPATI, Sreenath , NICKERSON, Brian , WONG, Samuel , CHAUDHARI, Sunil , LIU, Jonathan
发明人： KURUPATI, Sreenath , NICKERSON, Brian , WONG, Samuel , CHAUDHARI, Sunil , LIU, Jonathan
IPC分类号： G06T3/40
CPC分类号： G06T3/403
摘要： A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.
摘要翻译：一种用于视频后处理中的硬件边缘处理的方法和装置。在一个实施例中，该方法包括在输出像素计算期间识别计算输出像素所需的至少一个未输入输入像素。一旦被识别，根据检测到的边缘处理模式，为至少一个未填充的输入像素生成像素值。在一个实施例中，如果无输入输入像素的位置在像素帧边界之外，则执行无输入输入像素的像素值的生成。例如，在一个实施例中，对于缩放操作的输出像素计算，帧边界包括左边（上）边和右（底）边，对于边缘边缘或其附近计算输出像素所需的输入像素存在。描述和要求保护其他实施例。

5. 发明申请

WO2010077913A2 METHOD AND APPARATUS FOR NOISE REDUCTION IN VIDEO 审中-公开
标题翻译：在视频中减少噪声的方法和装置
公开(公告)号：WO2010077913A2
公开(公告)日：2010-07-08
申请号：PCT/US2009/068185
申请日：2009-12-16
申请人： INTEL CORPORATION , NESTARES, Oscar , HAUSSECKER, Horst, W. , ETTINGER, Scott, M. , GAT, Yoram , KURUPATI, Sreenath
发明人： NESTARES, Oscar , HAUSSECKER, Horst, W. , ETTINGER, Scott, M. , GAT, Yoram , KURUPATI, Sreenath
IPC分类号： G06T5/00 , H04N5/21
CPC分类号： G06T5/50 , G06T5/002 , G06T2207/10016 , G06T2207/20028
摘要： In some embodiments, a method of processing a video sequence may include receiving an input video sequence having an input video sequence resolution, aligning images from the input video sequence, reducing noise in the aligned images, and producing an output video sequence from the reduced noise images, wherein the output video sequence has the same resolution as the input video sequence resolution. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，处理视频序列的方法可以包括接收具有输入视频序列分辨率的输入视频序列，对来自输入视频序列的图像，减少对准图像中的噪声，以及从降低的噪声产生输出视频序列图像，其中输出视频序列具有与输入视频序列分辨率相同的分辨率。公开和要求保护其他实施例。

6. 发明申请

WO2008024668A1 DISPLAY PROCESSING LINE BUFFERS INCORPORATING PIPELINE OVERLAP 审中-公开
标题翻译：显示处理线缓冲器管道管叠加
公开(公告)号：WO2008024668A1
公开(公告)日：2008-02-28
申请号：PCT/US2007/076089
申请日：2007-08-16
申请人： INTEL CORPORATION , KURUPATI, Sreenath
发明人： KURUPATI, Sreenath
IPC分类号： G06F3/12 , H04N5/66
CPC分类号： G06T1/60 , G06T5/20 , G09G5/393 , H04N5/21
摘要： Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.
摘要翻译：公开了一种用于显示处理线缓冲器的装置，系统和方法，其中包括管道重叠。例如，公开了包括使用像素处理算法来处理图像的第一部分的像素值的处理逻辑以及耦合到处理逻辑的行缓冲器的装置。行缓冲器保持与第一部分相邻的图像的其他部分的至少一些像素值。其中由行缓冲器保持的图像的其他部分的像素值对应于由像素处理算法与第一部分的像素值进行卷积的图像的相邻部分的像素值。还公开了其他实施方式。

7. 发明申请

WO2013095447A1 PERCEPTUAL LOSSLESS COMPRESSION OF IMAGE DATA FOR TRANSMISSION ON UNCOMPRESSED VIDEO INTERCONNECTS 审中-公开
标题翻译：不可视视频互连传输图像数据的无损无损压缩
公开(公告)号：WO2013095447A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066554
申请日：2011-12-21
申请人： INTEL COPRORATION , KURUPATI, Sreenath , TRAW, C. Brendan, S.
发明人： KURUPATI, Sreenath , TRAW, C. Brendan, S.
IPC分类号： H04N5/91 , H04N7/24
CPC分类号： H04N19/00569 , G06F3/1454 , G09G5/006 , G09G2340/02 , G09G2350/00 , G09G2370/04 , G09G2370/12 , G09G2370/14 , G09G2370/16 , H04N19/124 , H04N19/182 , H04N19/503 , H04N19/593 , H04N21/4122 , H04N21/43635
摘要： Methods and systems may include a transmit apparatus and a receive apparatus. The transmit apparatus can have a first uncompressed video interconnect and an image encoder to generate a compressed bit stream based on an input pixel signal. The image encoder may also send the compressed bit stream to the first uncompressed video interconnect. The receive apparatus may have a second uncompressed video interconnect and an image decoder to receive the compressed bit stream from the second uncompressed video interconnect. The image decoder may also generate an output pixel signal based on the compressed bit stream.
摘要翻译：方法和系统可以包括发送装置和接收装置。发送装置可以具有第一未压缩视频互连和图像编码器，以基于输入像素信号生成压缩比特流。图像编码器还可以将压缩比特流发送到第一未压缩视频互连。接收设备可以具有第二未压缩视频互连和图像解码器，用于从第二未压缩视频互连接收压缩比特流。图像解码器还可以基于压缩比特流生成输出像素信号。

8. 发明申请

WO2003081598A3 METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH 审中-公开
公开(公告)号：WO2003081598A3
公开(公告)日：2003-10-02
申请号：PCT/US2003/007914
申请日：2003-03-13
申请人： INTEL CORPORATION
发明人： KURUPATI, Sreenath
IPC分类号： G11C7/10
摘要： A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

9. 发明申请

WO2003081598A2 METHOD AND SYSTEM FOR MAXIMIZING DRAM MEMORY BANDWIDTH 审中-公开
标题翻译：最大化DRAM存储器带宽的方法和系统
公开(公告)号：WO2003081598A2
公开(公告)日：2003-10-02
申请号：PCT/US2003/007914
申请日：2003-03-13
申请人： INTEL CORPORATION
发明人： KURUPATI, Sreenath
IPC分类号： G11C7/10
CPC分类号： G11C7/1087 , G11C7/1078 , G11C11/4082 , G11C11/4087 , G11C11/4093
摘要： A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.
摘要翻译：提供了一种用于最大化DRAM存储器带宽的方法和系统。该系统包括用于存储多个数据单元的多个缓冲器，耦合到缓冲器以选择数据单元将被存储到的缓冲器的选择器以及耦合到缓冲器以调度对应基于存储数据单元的缓冲区的存储体的数量。系统接收数据单元，基于数据单元的至少一部分计算索引，基于索引选择存储数据单元的缓冲器，将数据单元存储在选择的缓冲器中，调度存储器组访问根据索引，从所选缓冲区中读取数据单元，并访问存储区。

10. 发明申请

WO2003081857A1 VLAN TABLE MANAGEMENT FOR MEMORY EFFICIENT LOOKUPS AND INSERTS IN HARDWARE-BASED PACKET SWITCHES 审中-公开
标题翻译：基于硬件的分组交换机中的存储器有效查询和插入的VLAN表管理
公开(公告)号：WO2003081857A1
公开(公告)日：2003-10-02
申请号：PCT/US2003/006641
申请日：2003-03-04
申请人： INTEL CORPORATION
发明人： NAVADA, Muraleedhara , KURUPATI, Sreenath
IPC分类号： H04L12/56
CPC分类号： H04L12/4645 , H04L45/745
摘要： Described herein is a method and apparatus for memory efficient fast VLAN lookups and inserts in hardware-based packet switches. A table management engine (TME) is introduced into the switches to accelerate date searches and management. The TME manages a memory which is devided into two tables, one containing the data entries ("data entry table" 203), one containing the pointers and validity bits ("pointer table" 205). The TME comprises a reader/hasher (206), an executive table engine (208), a free list engine (210) and a control element (214). The reader/hasher obtains content from a key, which can be a VLAN rule. The executive table engine uses the kex content to address a pointer location in memory to retrieve the data. The executive table engine is also responsible for writing /deleting data into the memory and for pointers management.
摘要翻译：这里描述了一种用于存储器高效的快速VLAN查找和基于硬件的分组交换机中的插入的方法和装置。交换机中引入了表管理引擎（TME），以加速日期搜索和管理。 TME管理一个分为两个表的存储器，一个包含数据条目（“数据条目表”203），一个包含指针和有效位（“指针表”205））。 TME包括读取器/哈希器（206），执行表引擎（208），自由列表引擎（210）和控制元件（214）。读取器/哈希器从一个密钥获取内容，这可以是一个VLAN规则。执行表引擎使用kex内容来寻址内存中的指针位置来检索数据。执行表引擎还负责将数据写入/删除到存储器中并进行指针管理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式