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1. 发明申请

WO2013101125A1 PROTECTING THE INTEGRITY OF BINARY TRANSLATED CODE 审中-公开
标题翻译：保护二进制翻译代码的完整性
公开(公告)号：WO2013101125A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067974
申请日：2011-12-29
申请人： INTEL CORPORATION , RAIKIN, Shlomo , RAPPOPORT, Lihu , NUZMAN, Joseph
发明人： RAIKIN, Shlomo , RAPPOPORT, Lihu , NUZMAN, Joseph
IPC分类号： G06F9/30 , G06F9/305 , G06F15/80 , G06F13/38
CPC分类号： G06F8/41 , G06F8/52 , G06F21/64
摘要： The technologies provided herein relate to protecting the integrity of original code that has been optimized. For example, a processor may perform a fetch operation to obtain specified code from a memory. During execution, the code may be optimized and stored in a portion of the memory. The processor may obtain the optimized code from the portion of the memory. An entry of a first table may be modified to indicate a relationship between the particular code and the optimized code. One or more entries of a second table may be modified to specify the one or more physical memory locations. Each of the one or more entries of the second table may correspond to the entry of the first table. The processor may execute the optimized code when each of the one or more entries of the second table are valid.
摘要翻译：本文提供的技术涉及保护已经优化的原始代码的完整性。例如，处理器可以执行取出操作以从存储器获得指定的代码。在执行期间，代码可以被优化并存储在存储器的一部分中。处理器可以从存储器的一部分获得优化的代码。可以修改第一表的条目以指示特定代码和优化的代码之间的关系。可以修改第二表的一个或多个条目以指定一个或多个物理存储器位置。第二表中的一个或多个条目中的每一个可对应于第一表的条目。当第二表的一个或多个条目中的每一个有效时，处理器可以执行优化的代码。

2. 发明申请

WO2013101026A1 MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES 审中-公开
标题翻译：多级跟踪高速缓存线路的使用状态
公开(公告)号：WO2013101026A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067747
申请日：2011-12-29
申请人： INTEL CORPORATION , KIM, Ilhyun , KOREN, Chen (CK) , FARCY, Alexandre, J. , HINTON, Robert, L. , KHOR, Choon, Wei , RAPPOPORT, Lihu
发明人： KIM, Ilhyun , KOREN, Chen (CK) , FARCY, Alexandre, J. , HINTON, Robert, L. , KHOR, Choon, Wei , RAPPOPORT, Lihu
IPC分类号： G06F9/06 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30079 , G06F9/30047 , G06F9/3814
摘要： This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
摘要翻译：该公开内容包括跟踪高速缓存行的使用状态以提高管道的吞吐量，从而提高处理器的性能。可以使用第一阵列中的使用中的阵列跟踪存储在指令高速缓存中的多组指令的访问数据，直到这些集合中的一个或多个的数据达到阈值条件。然后可以使用第二阵列作为使用中阵列，以便在将微操作插入流水线之后跟踪指令集。当微操作从管道退出时，可以清除第一个阵列。该过程可能在第二个阵列达到阈值条件之后重复。在跟踪期间，可以通过检查每个阵列中的相应位来检测用于指令行的使用状态。附加阵列也可用于跟踪使用状态。

3. 发明申请

WO2010056511A3 TECHNIQUE FOR PROMOTING EFFICIENT INSTRUCTION FUSION 审中-公开
公开(公告)号：WO2010056511A3
公开(公告)日：2010-05-20
申请号：PCT/US2009/062219
申请日：2009-10-27
申请人： INTEL CORPORATION , OUZIEL, Ido , RAPPOPORT, Lihu , VALENTINE, Robert , GABOR, Ron , RAGHUVANSHI, Pankaj
发明人： OUZIEL, Ido , RAPPOPORT, Lihu , VALENTINE, Robert , GABOR, Ron , RAGHUVANSHI, Pankaj
IPC分类号： G06F9/06 , G06F9/22 , G06F9/30
摘要： A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

4. 发明申请

WO2010053837A3 OPTIMIZING PERFORMANCE OF INSTRUCTIONS BASED ON SEQUENCE DETECTION OR INFORMATION ASSOCIATED WITH THE INSTRUCTIONS 审中-公开
公开(公告)号：WO2010053837A3
公开(公告)日：2010-05-14
申请号：PCT/US2009/062736
申请日：2009-10-30
申请人： INTEL CORPORATION , FALIK, Ohad , RAPPOPORT, Lihu , GABOR, Ron , KUROLAP, Yulia , MISHAELI, Michael
发明人： FALIK, Ohad , RAPPOPORT, Lihu , GABOR, Ron , KUROLAP, Yulia , MISHAELI, Michael
IPC分类号： G06F9/06 , G06F9/30
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

5. 发明申请

WO2018111228A1 APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2018111228A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066242
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

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