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1. 发明申请

WO2011075246A3 INSTRUCTION FOR ENABLING A PROCESSOR WAIT STATE 审中-公开
公开(公告)号：WO2011075246A3
公开(公告)日：2011-06-23
申请号：PCT/US2010/056320
申请日：2010-11-11
申请人： INTEL CORPORATION , DIXON, Martin G. , RODGERS, Scott D. , GUNTHER, Stephen H. , SETHI, Prashant , BAHRAMI, Taraneh , HAMMARLUND, Per
发明人： DIXON, Martin G. , RODGERS, Scott D. , GUNTHER, Stephen H. , SETHI, Prashant , BAHRAMI, Taraneh , HAMMARLUND, Per
IPC分类号： G06F9/30 , G06F9/46 , G06F1/32
摘要： In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

2. 发明申请

WO2013090348A1 A METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING CONFIGURABLE MAXIMUM PROCESSOR CURRENT 审中-公开
标题翻译：一种用于能源效率和能源保护的方法，装置和系统，包括可配置的最大处理器电流
公开(公告)号：WO2013090348A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/069121
申请日：2012-12-12
申请人： INTEL CORPORATION , SHAH, Ketan R. , DISTEFANO, Eric , GUNTHER, Stephen H. , SHRALL, Jeremy J.
发明人： SHAH, Ketan R. , DISTEFANO, Eric , GUNTHER, Stephen H. , SHRALL, Jeremy J.
IPC分类号： G06F13/14 , G06F1/32
CPC分类号： G06F1/3243 , G06F1/3206 , G06F1/324 , G06F9/4401 , G06F9/4411 , G06F9/455 , Y02D10/126 , Y02D10/152 , Y02D50/20
摘要： An apparatus, method and system is described herein for providing multiple maximum current configuration options including corresponding turbo frequencies for a processing device. Available options for a processor are determined by initialization code. And based on platform electrical capabilities, an optimal one of the multiple current configuration options is selected. Moreover, during runtime another current configuration is dynamically selected based on current configuration considerations to provide high flexibility and best possible performance per part and computing platform.
摘要翻译：本文描述了一种用于提供多个最大电流配置选项的装置，方法和系统，包括用于处理设备的对应的turbo频率。处理器的可用选项由初始化代码确定。并且基于平台电气功能，选择多个当前配置选项中的最佳一个。此外，在运行期间，基于当前配置注意事项动态地选择当前配置，以提供每个部件和计算平台的高灵活性和最佳性能。

3. 发明申请

WO2023081567A1 SOFTWARE THREAD-BASED DYNAMIC MEMORY BANDWIDTH ALLOCATION 审中-公开
公开(公告)号：WO2023081567A1
公开(公告)日：2023-05-11
申请号：PCT/US2022/077671
申请日：2022-10-06
申请人： INTEL CORPORATION , MATHIYALAGAN, Vijay Anand , GUNTHER, Stephen H. , KHATAKALLE, Shidlingeshwar , CHINNAKKONDA VIDYAPOORNACHARY, Diyanesh Babu
发明人： MATHIYALAGAN, Vijay Anand , GUNTHER, Stephen H. , KHATAKALLE, Shidlingeshwar , CHINNAKKONDA VIDYAPOORNACHARY, Diyanesh Babu
IPC分类号： G06F9/48 , G06F9/50 , G06F9/30 , G06F1/329 , G06F1/3225
摘要： Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.

4. 发明申请

WO2014051780A1 APPARATUS AND METHOD FOR DETERMINING THE NUMBER OF EXECUTION CORES TO KEEP ACTIVE IN A PROCESSOR 审中-公开
标题翻译：用于确定处理器中执行线数量保持有效的装置和方法
公开(公告)号：WO2014051780A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047629
申请日：2013-06-25
申请人： INTEL CORPORATION , ANANTHAKRISHNAN, Avinash N. , SEBOT, Julien Fefe , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SAMSON, Eric C.
发明人： ANANTHAKRISHNAN, Avinash N. , SEBOT, Julien Fefe , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SAMSON, Eric C.
IPC分类号： G06F1/26 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/324 , G06F1/3287 , Y02D10/122 , Y02D10/126 , Y02D10/171
摘要： A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.
摘要翻译：描述了包括多个执行核心的处理器。处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使得处理器以基本上线性的功率消耗与频率操作区域相互作用，使得作为功率消耗的功能的性能增益与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。

5. 发明申请

WO2014099026A1 CONTROLLING CONFIGURABLE PEAK PERFORMANCE LIMITS OF A PROCESSOR 审中-公开
标题翻译：控制处理器的可配置峰值性能限制
公开(公告)号：WO2014099026A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/048455
申请日：2013-06-28
申请人： INTEL CORPORATION
发明人： SHRALL, Jeremy J. , GUNTHER, Stephen H. , SISTLA, Krishnakanth V. , WELLS, Ryan D. , CONRAD, Shaun M.
IPC分类号： G06F1/32 , G06F9/38 , G06F9/46
CPC分类号： G06F1/3243 , G06F1/324 , G06F3/14 , Y02D10/152
摘要： In one embodiment, the present invention includes a processor having a plurality of cores each to execute instructions, a non-volatile storage to store maximum peak operating frequency values each a function of a given number of active cores, a configuration storage to store frequency limits each corresponding to one of the maximum peak operating frequency values or a configurable clip frequency value less than the maximum peak operating frequency value. In turn, a power controller is configured to limit operating frequency of the cores to a corresponding frequency limit obtained from the configuration storage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有多个核的处理器，每个核每个用于执行指令;非易失性存储器，用于存储最大峰值操作频率值，每一个是给定数量的活动核心的功能;存储频率限制的配置存储每个对应于最大峰值工作频率值之一或可配置的剪辑频率值小于最大峰值工作频率值。反过来，功率控制器被配置为将芯的操作频率限制到从配置存储获得的相应频率限制。描述和要求保护其他实施例。

6. 发明申请

WO2018111228A1 APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE 审中-公开
公开(公告)号：WO2018111228A1
公开(公告)日：2018-06-21
申请号：PCT/US2016/066242
申请日：2016-12-12
申请人： INTEL CORPORATION
发明人： BRANDT, Jason W. , CHAPPELL, Robert S. , CORBAL, Jesus , GROCHOWSKI, Edward T. , GUNTHER, Stephen H. , GUY, Buford M. , HUFF, Thomas R. , HUGHES, Christopher J. , OULD-AHMED-VALL, Elmoustapha , SINGHAL, Ronak , SOTOUDEH, Seyed Yahya , TOLL, Bret L. , RAPPOPORT, Lihu , PAPWORTH, David , ALLEN, James D.
IPC分类号： G06F12/0817
摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

7. 发明申请

WO2014035542A1 PERFORMING CROSS-DOMAIN THERMAL CONTROL IN A PROCESSOR 审中-公开
标题翻译：在处理器中执行跨域热控制
公开(公告)号：WO2014035542A1
公开(公告)日：2014-03-06
申请号：PCT/US2013/048045
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： MAN, Xiuting C. , DERR, Michael N. , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , CONRAD, Shaun M. , ANANTHAKRISHNAN, Avinash N.
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有至少一个核的执行指令的第一域和耦合到第一域并且包括至少一个非核心电路的第二域。这些域可以在独立频率下操作，并且耦合到域的功率控制单元可以包括热逻辑，以响应于第二域中的热事件的发生而引起第一域的频率的降低。描述和要求保护其他实施例。

8. 发明申请

WO2013086042A1 A METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING BALANCING POWER AMONG MULTI-FREQUENCY DOMAINS OF A PROCESSOR BASED ON EFFICIENCY RATING SCHEME 审中-公开
标题翻译：基于效率评估方案的处理器多频域的能量效率和能源保护的方法，装置和系统，包括平衡功率
公开(公告)号：WO2013086042A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/068024
申请日：2012-12-05
申请人： INTEL CORPORATION
发明人： KIM, Seongwoo , SHRALL, Jeremy , SCHWARTZ, Jay D. , GUNTHER, Stephen H. , FURRER, Travis C.
IPC分类号： G06F1/32 , G06F9/06
CPC分类号： G06F1/329 , G06F1/3206 , G06F11/3466 , Y02D10/24
摘要： The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor * alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.
摘要翻译：可以比较处理器中每个域的效率等级（ER），然后基于域的ER来在域中有效地分配功率预算。对于给定的功率预算，ER可以指示域之间的性能回报方面的相对优势，即如果ER对于域更高，则在功率利用中可以预期更高的有效性。域的ER可以定义为（可扩展性因子/成本因子*α）。可扩展性因素可以被定义为由提供给域的时钟频率（以％计）的增加而导致的性能增加（以％计）。成本因子可以被定义为使得提供给域的时钟频率增加所需的功率预算值，而α是调整因子。

9. 发明申请

WO2021040951A1 SYSTEM, APPARATUS AND METHOD FOR PROVIDING HARDWARE STATE FEEDBACK TO AN OPERATING SYSTEM IN A HETEROGENEOUS PROCESSOR 审中-公开
公开(公告)号：WO2021040951A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/043978
申请日：2020-07-29
申请人： INTEL CORPORATION
发明人： GUPTA, Praveen Kumar , ANANTHAKRISHNAN, Avinash N. , GORBATOV, Eugene , GUNTHER, Stephen H.
IPC分类号： G06F1/329 , G06F1/3237 , G06F1/3206 , G06F9/50
摘要： In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine maximum operating points for the cores based at least in part on the scaled power budget; determine efficiency values for the cores based at least in part on the maximum operating points; and report a hardware state change to an operating system scheduler based on the efficiency values. Other embodiments are described and claimed.

10. 发明申请

WO2014105194A1 INDEPENDENT CONTROL OF PROCESSOR CORE RETENTION STATES 审中-公开
标题翻译：处理器核心保持状态的独立控制
公开(公告)号：WO2014105194A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048306
申请日：2013-06-27
申请人： INTEL CORPORATION
发明人： CONRAD, Shaun M. , GUNTHER, Stephen H. , SHRALL, Jeremy J. , DEVAL, Anant S. , JAHAGIRDAR, Sanjeev S.
IPC分类号： G06F9/38 , G06F9/46 , G06F1/32
CPC分类号： G06F1/3296 , G06F1/3243 , Y02D10/152 , Y02D10/172
摘要： In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括第一处理器核心，第二处理器核心，第一电压调节器，以在第一处理器核心活动时向第一处理器核心提供具有第一有效值的第一电压;以及第二电压调节器当第二处理器核心活动时，向第二处理器核心提供具有第二有效值的第二电压。响应于将第一处理器核放置在具有相关联的第一低功率电压值的第一低功率状态的请求，第一电压调节器将第一电压降低到小于第一低功率电压的第二低功率电压值电压值，独立于第二电压调节器。存储在第一处理器核心的第一寄存器中的第一数据保持在第二低功率值。描述和要求保护其他实施例。

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