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1. 发明申请

WO2020005439A8 APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY OF CLOCK AND VOLTAGES 审中-公开
公开(公告)号：WO2020005439A8
公开(公告)日：2020-01-02
申请号：PCT/US2019/034213
申请日：2019-05-28
申请人： INTEL CORPORATION
发明人： KURD, Nasser , MOSALIKANTI, Praveen , HEGDE, Thripthi , NEIDENGARD, Mark L. , GROSSNICKLE, Vaughn J. , WANG, Qi , RAMESH, Kandadai
IPC分类号： G06F21/81 , G06F21/71 , G06F1/06 , G06F1/28
摘要： An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.

2. 发明申请

WO2019182697A1 APPARATUS TO IMPROVE LOCK TIME OF A FREQUENCY LOCKED LOOP 审中-公开
公开(公告)号：WO2019182697A1
公开(公告)日：2019-09-26
申请号：PCT/US2019/018104
申请日：2019-02-14
申请人： INTEL CORPORATION
发明人： MOSALIKANTI, Praveen , WANG, Qi , NEIDENGARD, Mark L. , GROSSNICKLE, Vaughn J. , KURD, Nasser
IPC分类号： H03L7/099 , H03K3/03 , H03K5/134
摘要： An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.

3. 发明申请

WO2015041645A1 QUADRATURE DIVIDER 审中-公开
标题翻译：四分法师
公开(公告)号：WO2015041645A1
公开(公告)日：2015-03-26
申请号：PCT/US2013/060419
申请日：2013-09-18
申请人： INTEL CORPORATION , NEIDENGARD, Mark L. , WANG, Qi
发明人： NEIDENGARD, Mark L. , WANG, Qi
IPC分类号： H03L7/00
CPC分类号： H03K3/037 , H03K5/15 , H03K23/588
摘要： Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.
摘要翻译：描述了正交分频器的装置。该装置独立于卡锁锁存器，并且用于产生正交时钟。该装置包括：由时钟信号控制的第一选择单元，第一选择单元直接或间接产生正交时钟的第一相位; 由所述时钟信号控制的第三选择单元，所述第三选择单元接收所述正交时钟的第一相位，所述第三选择单元直接或间接产生所述正交时钟的第三相位，其中所述第一选择单元接收所述第三选择单元，正交时钟的相位。

4. 发明申请

WO2020005439A1 APPARATUS FOR AUTONOMOUS SECURITY AND FUNCTIONAL SAFETY CLOCK AND VOLTAGES 审中-公开
公开(公告)号：WO2020005439A1
公开(公告)日：2020-01-02
申请号：PCT/US2019/034213
申请日：2019-05-28
申请人： INTEL CORPORATION
发明人： KURD, Nasser , MOSALIKANTI, Praveen , HEGDE, Thripthi , NEIDENGARD, Mark L. , GROSSNICKLE, Vaughn J. , WANG, Qi , RAMESH, Kandadai
IPC分类号： G06F21/81 , G06F21/71 , G06F1/06 , G06F1/28
摘要： An apparatus is provided for autonomous security and functional safety (FUSA) of clock and voltages. The apparatus may include: a multiplexer having a first input communicatively coupled to a pin to receive a first clock external to a die, and a second input coupled to an output of a divider; an oscillator to provide a second clock; and a counter coupled to an output of the multiplexer and the oscillator, wherein the counter is to operate with the second clock and is to determine a frequency of the first clock. The apparatus may further include a voltage monitor circuitry for monitoring voltage(s) for FUSA, a reference generator for FUSA, a duty cycle monitor for FUSA, a frequency degradation monitor for FUSA, and a phase error degradation monitor for FUSA.

5. 发明申请

WO2013082752A1 METHOD AND SYSTEM FOR IMPROVING RESPONSIVENESS IN A VEHICLE COMPUTING PLATFORM 审中-公开
标题翻译：用于改善车辆计算平台响应的方法和系统
公开(公告)号：WO2013082752A1
公开(公告)日：2013-06-13
申请号：PCT/CN2011/083522
申请日：2011-12-06
申请人： INTEL CORPORATION , WANG, Qi , WANG, Jian , SHANG, Yaohui , ROTHMAN, Michael, A. , ZIMMER, Vincent, J.
发明人： WANG, Qi , WANG, Jian , SHANG, Yaohui , ROTHMAN, Michael, A. , ZIMMER, Vincent, J.
IPC分类号： G06F13/24
CPC分类号： H04N1/00209 , B60R1/002 , B60R11/04 , B60R2300/802 , B60W30/18036 , B60W50/06 , B60W2420/42 , G06F13/24 , H04N1/00095 , H04N2101/00
摘要： A method and system for improving responsiveness of a vehicle computing platform includes enabling a camera feature during the pre-boot phase of a computing device and using a special-purpose operating mode of the computing device to initiate the streaming of camera image data to a display.
摘要翻译：一种用于改善车辆计算平台的响应性的方法和系统包括在计算设备的预引导阶段启用相机特征，并且使用计算设备的专用操作模式来启动将相机图像数据流传输到显示器。

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