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1. 发明申请

WO1998020414A1 METHOD FOR SUPPORTING A VARIETY OF INSTRUCTION FETCH UNITS IN A PIPELINE WITH A SINGLE MICROPROCESSOR CORE 审中-公开
标题翻译：在单管微核心核心的管道中支持各种指导设备单元的方法
公开(公告)号：WO1998020414A1
公开(公告)日：1998-05-14
申请号：PCT/US1997013504
申请日：1997-07-30
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MEYER, Paul, G. , STRAZDUS, Stephen , O'CONNOR, Dennis , ADELMEYER, Thomas , HEEB, Jay , TOPPS, Avery
IPC分类号： G06F09/30
CPC分类号： G06F9/3802 , G06F9/3867
摘要： A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage (52) and a decoding stage (55). The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit (59). The instruction fetch unit (59) fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipeline is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.
摘要翻译：适用于各种指令提取单元的处理器核心。处理器核心包括多个管级，包括指令指针产生级（52）和解码级（55）。核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。捆绑包在核心外部传送到指令提取单元（59）。指令获取单元（59）获取指令并将其添加到捆绑包中，然后在核心内向下流出管道之前转发捆绑包。以这种方式，引入外部管道，提供核心中的不连续管段之间的连接。此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

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