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    • 3. 发明申请
    • APPARATUS, SYSTEM AND METHOD FOR CACHING COMPRESSED DATA BACKGROUND
    • 用于缓存压缩数据的装置,系统和方法背景技术
    • WO2016099664A1
    • 2016-06-23
    • PCT/US2015/057815
    • 2015-10-28
    • INTEL CORPORATION
    • TRIKA, Sanjeev N.GARCIA, Rowel S.
    • G06F12/08G06F12/02
    • G06F12/0802G06F12/0871G06F12/0886G06F2212/1016G06F2212/1044G06F2212/222G06F2212/401G06F2212/7201G06F2212/7203
    • Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.
    • 基于这种数据的压缩来有效地缓存数据的技术和机制。 本公开的技术包括缓存系统,方法和计算机可读介质,用于支持在将高速缓冲存储器中的高速缓存行写入之前被压缩的数据执行的操作。 在一些实施例中,高速缓存控制器确定要作为高速缓存行存储的压缩数据的大小。 高速缓存控制器识别逻辑块地址(LBA)范围以缓存压缩数据,其中这种标识基于压缩数据的大小以及描述高速缓冲存储器的多个LBA范围的参考信息。 一个或多个这样的LBA范围具有不同的相应尺寸。 在其他实施例中,高速缓存存储器的LBA范围同时存储相应的压缩高速缓存行,其中LBA范围并且具有不同的相应尺寸。