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1. 发明申请

WO0146989A3 DECOUPLING CAPACITORS FOR THIN GATE OXIDES 审中-公开
标题翻译：用于薄栅氧化物的去除电容器
公开(公告)号：WO0146989A3
公开(公告)日：2002-05-10
申请号：PCT/US0031352
申请日：2000-11-13
申请人： INTEL CORP , KESHAVARZI ALI , VIVEK K DE , KARNIK TANAY , NAIR RAJENDRAN
发明人： KESHAVARZI ALI , DE VIVEK K , KARNIK TANAY , NAIR RAJENDRAN
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H01L29/94 , H01L27/06
CPC分类号： H01L27/0805 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
摘要翻译：在一些实施例中，本发明涉及具有承载电源电压的第一导体和承载接地电压的第二导体的管芯。以耗尽模式工作的半导体电容器耦合在第一和第二导体之间，以在第一和第二导体之间提供去耦电容，半导体电容器具有栅极电压。可以使用各种配置，包括：n体中的n +栅极多晶硅和n +源极/漏极区域; p +栅极多晶硅和n +源极/漏极区域; p +栅极poly和p +源极/漏极区域在n体中; p体中的p +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和p +源极/漏极区域; p体中的n +栅极多晶硅和n +源极/漏极区域。电源电压可能比平带电压具有更大的绝对值。

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