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    • 3. 发明申请
    • NANOWIRE DEVICE WITH (111) VERTICAL SIDEWALLS AND METHOD OF FABRICATION
    • 具有(111)垂直边的纳米器件和制造方法
    • WO2006083310A3
    • 2006-10-05
    • PCT/US2005022699
    • 2005-06-28
    • HEWLETT PACKARD DEVELOPMENT COISLAM SAIFUL MCHEN YONGWANG SHIH-YUAN
    • ISLAM SAIFUL MCHEN YONGWANG SHIH-YUAN
    • B81B7/00
    • H01L27/1203B82Y10/00G11C2213/81H01L29/045H01L29/0665H01L29/0673H01L29/861
    • A nano-scale device 10, 20, 30, 60 and method 40, 50, 70 of fabrication provide a nanowire 14, 24, 34, 64 having (111) vertical sidewalls 14a, 22e, 34a, 64a. The nano-scale device includes a semiconductor-on-insulator substrate 12, 22, 32, 62 polished in a [110] direction, the nanowire, and an electrical contact 26, 35 at opposite ends of the nanowire 24, 34. The method 40, 50, 70 includes wet etching 42, 52, 72 a semiconductor layer 12a, 22a, 32a. 62a of the semiconductor-on-insulator substrate to form 44, 54 the nanowire 24, 34 extending between a pair of islands 22f, 32f in the semiconductor layer 22a, 32a. The method 50 further includes depositing 56 an electrically conductive material on the pair of islands to form the electrical contacts 26, 36. A nano-pn diode 60 includes the nanowire 64 as a first nano-electrode, a pn-junction 66 verically stacked on the nanowire 64, and a second nano-electrode 68 on a (110) horizontal planar end of the pn-junction. The nano-pn diode 60 may be fabricated in array of the diodes on the semiconductor-on-insulator substrate 62.
    • 具有(111)垂直侧壁14a,22e,34a,64a的纳米级器件10,20,30,60和制造方法40,50,70制成纳米线14,24,34,64。 纳米级器件包括在[110]方向上抛光的绝缘体上半导体衬底12,22,32,62,纳米线和在纳米线24,34的相对端的电接触26,35。 40,50,70包括湿蚀刻42,52,72半导体层12a,22a,32a。 62a,以形成44,54在半导体层22a,32a中的一对岛状物22f,32f之间延伸的纳米线24,34。 方法50还包括在该对岛上沉积56导电材料以形成电接触26,36。纳米pn二极管60包括作为第一纳米电极的纳米线64, 纳米线64和在pn结的(110)水平平面端上的第二纳米电极68。 可以在绝缘体上半导体衬底62上的二极管的阵列中制造纳米pn二极管60。
    • 6. 发明申请
    • NANOSCALE ELECTRIC LITHOGRAPHY
    • WO2005070167A8
    • 2006-12-07
    • PCT/US2005000901
    • 2005-01-12
    • UNIV CALIFORNIACHEN YONG
    • CHEN YONG
    • G03F7/00
    • B82Y10/00B82Y30/00B82Y40/00G03F7/0002G03G13/28G03G13/283G03G13/286
    • A nanoscale lithographic method in which a reusable conductive mask, having a pattern of conductive surfaces and insulating surfaces, is positioned upon a substrate whose surface contains an electrically responsive resist layer over a buried conductive layer. When an electric field is applied between the conductive mask and buried conductive layer, the resist layer is altered in portions adjacent the conductive areas of the mask. Selective processing is performed on the surface of the substrate, alter mask removal, to remove portions of the resist layer according to the pattern transferred from the mask. The substrate may be a target substrate, or the substrate may be utilized for a lithographic masking step of another substrate. In one aspect of the invention the electrodes to which the charge is applied are divided, such as into a plurality of rows and columns wherein any desired pattern may be created without the need to fabricate specific masks.
    • 一种纳米级光刻方法,其中具有导电表面和绝缘表面图案的可重复使用的导电掩模位于其表面在掩埋导电层上包含电响应抗蚀剂层的基底上。 当在导电掩模和掩埋导电层之间施加电场时,抗蚀剂层在与掩模的导电区域相邻的部分中改变。 在基板的表面上进行选择性处理,改变掩模去除,以根据从掩模转印的图案去除抗蚀剂层的部分。 衬底可以是目标衬底,或者衬底可以用于另一衬底的光刻掩模步骤。 在本发明的一个方面,施加电荷的电极被分割成多个行和列,其中可以创建任何期望的图案,而不需要制造特定的掩模。
    • 8. 发明申请
    • ONE POT SYNTHESIS OF TETRAZOLE DERIVATIVES OF SIROLIMUS
    • 一锅法合成四螺旋四唑衍生物
    • WO2007094886A3
    • 2007-11-29
    • PCT/US2006061909
    • 2006-12-12
    • ABBOTT LABDHAON MADHUPHSIAO CHU-NUNGPATEL SUBHASHBONK PETERCHEMBURKAR SANJAYCHEN YONG
    • DHAON MADHUPHSIAO CHU-NUNGPATEL SUBHASHBONK PETERCHEMBURKAR SANJAYCHEN YONG
    • C07D498/18A61K31/395
    • C07D498/18
    • A single-step, one-pot process to obtain zotarolimus and other rapamycin derivatives on large scale that improves currently available syntheses. In one embodiment, dried rapamycin is dissolved in isopropylacetate . After cooling and 2,6-Lutidine addition, triflic anhydride is slowly added at -30° C. Salts are removed by filtration. Tetrazole, followed by a tert-base diisopropylethylamine is added. After incubation at room temperature, the product is concentrated and purified by a silica gel column using THF/heptane as eluant. The product is collected, concentrated, and purified using an acetone/heptane column. The product-containing fractions are concentrated. The product is dissolved in t-BME and precipitated with heptane. The solids are dissolved in acetone, treated with butylated-hydroxy toluene, and the solution concentrated. The process is repeated twice with acetone to remove solvents. At least one stabilizing agent is added, such as BHT at 0.5% before drying.
    • 大规模获得zotarolimus和其他雷帕霉素衍生物的单步一锅法工艺,改进了目前可用的合成方法。 在一个实施方案中,将干燥的雷帕霉素溶解在乙酸异丙酯中。 冷却并加入2,6-二甲基吡啶后,在-30℃缓慢加入三氟甲磺酸酐。过滤除去盐。 加入四唑,然后加入叔丁基二异丙基乙胺。 在室温下温育后,将产物浓缩并通过硅胶柱使用THF /庚烷作为洗脱液进行纯化。 收集产物,浓缩并使用丙酮/庚烷柱纯化。 含产物的级分被浓缩。 将产物溶解在t-BME中并用庚烷沉淀。 将固体溶于丙酮中,用丁基化羟基甲苯处理,浓缩溶液。 该过程用丙酮重复两次以除去溶剂。 在干燥前加入至少一种稳定剂,例如0.5%的BHT。
    • 9. 发明申请
    • NANOSCALE ELECTRIC LITHOGRAPHY
    • WO2005070167A3
    • 2007-05-31
    • PCT/US2005000901
    • 2005-01-12
    • UNIV CALIFORNIACHEN YONG
    • CHEN YONG
    • B41D7/00B05D1/00B05D3/00B41C1/06B41F9/00B41F33/00G03F7/00H01T14/00H05C1/04H05H1/48
    • B82Y10/00B82Y30/00B82Y40/00G03F7/0002G03G13/28G03G13/283G03G13/286
    • A nanoscale lithographic method in which a reusable conductive mask, having a pattern of conductive surfaces and insulating surfaces, is positioned upon a substrate whose surface contains an electrically responsive resist layer over a buried conductive layer. When an electric field is applied between the conductive mask and buried conductive layer, the resist layer is altered in portions adjacent the conductive areas of the mask. Selective processing is performed on the surface of the substrate, alter mask removal, to remove portions of the resist layer according to the pattern transferred from the mask. The substrate may be a target substrate, or the substrate may be utilized for a lithographic masking step of another substrate. In one aspect of the invention the electrodes to which the charge is applied are divided, such as into a plurality of rows and columns wherein any desired pattern may be created without the need to fabricate specific masks.
    • 一种纳米级光刻方法,其中具有导电表面和绝缘表面图案的可重复使用的导电掩模位于其表面在掩埋导电层上包含电响应抗蚀剂层的基底上。 当在导电掩模和掩埋导电层之间施加电场时,抗蚀剂层在与掩模的导电区域相邻的部分中改变。 在基板的表面上进行选择性处理,改变掩模去除,以根据从掩模转印的图案去除抗蚀剂层的部分。 衬底可以是目标衬底,或者衬底可以用于另一衬底的光刻掩模步骤。 在本发明的一个方面,施加电荷的电极被分割成多个行和列,其中可以创建任何期望的图案,而不需要制造特定的掩模。