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1. 发明申请

WO2019239109A1 METHOD, SYSTEM AND DEVICE FOR MEMORY DEVICE OPERATION 审中-公开
公开(公告)号：WO2019239109A1
公开(公告)日：2019-12-19
申请号：PCT/GB2019/051540
申请日：2019-06-04
申请人： ARM LTD
发明人： JELOKA, Supreet , DAS, Shidhartha , BHARGAVA, Mudit , SINHA, Saurabh Pijuskumar , MYERS, James Edward
IPC分类号： G11C13/00
摘要： The present techniques generally relate to methods, systems and devices for operation of memory device. In one embodiment, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the correlated electron element.

2. 发明申请

WO2018162874A1 A SPIKING NEURAL NETWORK 审中-公开
公开(公告)号：WO2018162874A1
公开(公告)日：2018-09-13
申请号：PCT/GB2018/050389
申请日：2018-02-13
申请人： ARM LTD
发明人： SUDA, Naveen , CHANDRA, Vikas , CLINE, Brian Tracy , SINHA, Saurabh Pijuskumar , DAS, Shidhartha
IPC分类号： G06N3/063 , G06N3/04
摘要： Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) elementor Correlated Electron Switch (CES) element.

3. 发明申请

WO2017220968A1 MONOLITHIC 3D INTEGRATED CIRCUITS WITH INTER-TIER VIAS 审中-公开
标题翻译：具有层间VIAS的单片3D集成电路
公开(公告)号：WO2017220968A1
公开(公告)日：2017-12-28
申请号：PCT/GB2017/051682
申请日：2017-06-09
申请人： ARM LTD
发明人： SINHA, Saurabh Pijuskumar , AITKEN, Robert Campbell , CLINE, Brian Tracy , YERIC, Gregory Munson , CHANG, Kyungwook
IPC分类号： H01L23/48 , H01L23/528 , H01L27/06
摘要： Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.
摘要翻译：这里描述的各种实现可以涉及在集成电路（IC）中使用层间过孔（IV）。在一个实现中，三维（3D）IC可以包括设置在衬底层上的多个层，其中层可以包括具有电耦合到第一互连层的第一有源器件层的第一层，并且还可以包括第二层具有电耦合到第二互连层的第二有源器件层，其中第一互连层包括最接近第一有源器件层的最上层。 3D IC可以进一步包括电耦合第二互连层和最上层的IV。最上层可以电耦合到第一层的外围位置处的电源，从而将电源电耦合到第一有源器件层和第二有源器件层。

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