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1. 发明申请

WO2020234557A1 STATISTICAL MODE DETERMINATION 审中-公开
公开(公告)号：WO2020234557A1
公开(公告)日：2020-11-26
申请号：PCT/GB2020/050793
申请日：2020-03-25
申请人： ARM LIMITED
发明人： ÖZER, Emre , KUFEL, Jedrzej , EYOLE, Mbou , BIGGS, John Philip
IPC分类号： G06F7/544 , G06F7/22 , G06F7/60
摘要： Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

2. 发明申请

WO2007031696A1 CACHE MISS DETECTION IN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理设备中的高速缓存检测
公开(公告)号：WO2007031696A1
公开(公告)日：2007-03-22
申请号：PCT/GB2005/003531
申请日：2005-09-13
申请人： ARM LIMITED , GHOSH, Mrinmoy , ÖZER, Emre , BILES, Stuard, David
发明人： GHOSH, Mrinmoy , ÖZER, Emre , BILES, Stuard, David
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0802 , G06F12/0897
摘要： A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a data value is required while executing a first program thread, the processing logic issues an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure to determine whether the data value is stored in the cache. Indication logic is provided which in response to an address portion of the address provides an indication as to whether the data value is stored in the cache, this indication being produced before a result of the lookup procedure is available, and the indication logic only issuing an indication that the data value is not stored in the cache if that indication is guaranteed to be correct. Control logic is then provided which, if the indication indicates that the data value is not stored in the cache, uses that indication to control a process having an effect on a program thread other than the first program thread.
摘要翻译：提供了一种用于检测高速缓存未命中的数据处理装置和方法。数据处理装置具有用于执行多个程序线程的处理逻辑，以及用于存储由处理逻辑进行访问的数据值的高速缓存。当执行第一程序线程时需要访问数据值时，处理逻辑发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓冲存储器响应于地址执行查找过程以确定是否数据值存储在缓存中。指示逻辑被提供，其响应于地址的地址部分提供关于数据值是否存储在高速缓存中的指示，该指示是在查找过程的结果可用之前产生的，并且指示逻辑仅发出指示如果该指示保证正确，则数据值不存储在高速缓存中。然后提供控制逻辑，如果该指示指示数据值未被存储在高速缓存中，则使用该指示来控制对除第一程序线程之外的程序线程有影响的进程。

3. 发明申请

WO2013061025A1 A DATA PROCESSING APPARATUS AND METHOD FOR ANALYSING TRANSIENT FAULTS OCCURRING WITHIN STORAGE ELEMENTS OF THE DATA PROCESSING APPARATUS 审中-公开
标题翻译：一种数据处理装置和方法，用于分析在数据处理装置的存储单元中发生的瞬时故障
公开(公告)号：WO2013061025A1
公开(公告)日：2013-05-02
申请号：PCT/GB2012/052204
申请日：2012-09-07
申请人： ARM LIMITED , ÖZER, Emre , SAZEIDES, Yiannakis , KERSHAW, Daniel , BILES, Stuart David
发明人： ÖZER, Emre , SAZEIDES, Yiannakis , KERSHAW, Daniel , BILES, Stuart David
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/1415 , G06F11/0727 , G06F11/076 , G06F11/0787 , G06F2201/86
摘要： A data processing apparatus and method are provided for analysing transient faults occurring within storage elements of the data processing apparatus. The data processing apparatus has a plurality of storage elements residing at different physical locations within the data processing apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry then monitors the global transient fault history data in order to determine based on predetermined criteria whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. Such an approach provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.
摘要翻译：提供了一种用于分析在数据处理装置的存储元件内发生的瞬态故障的数据处理装置和方法。数据处理装置具有驻留在数据处理装置内的不同物理位置处的多个存储元件，以及用于检测在每个存储元件中发生的局部瞬态故障的故障历史电路，以及用于基于检测到的局部瞬态来保持全局瞬态故障历史数据故障。分析电路然后监视全局瞬态故障历史数据，以便基于预定标准来确定全局瞬态故障历史数据是指示在数据处理装置内发生的随机瞬态故障，还是指示协调的瞬时故障攻击。分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。这种方法提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图规避数据处理设备的安全性时发起的协调的瞬态故障攻击。

4. 发明申请

WO2021191579A1 PACKAGING FOR A PHARMACEUTICAL PRODUCT 审中-公开
公开(公告)号：WO2021191579A1
公开(公告)日：2021-09-30
申请号：PCT/GB2021/050280
申请日：2021-02-08
申请人： ARM LIMITED
发明人： ÖZER, Emre
IPC分类号： A61J1/18 , B65D41/04 , A61J1/00 , A61J1/03 , A61J1/035 , A61J2200/70 , B65D17/02 , B65D2201/00 , B65D2211/00 , B65D2213/00 , B65D2215/00 , B65D25/08 , B65D51/24 , B65D51/248 , B65D79/02 , B65D81/2076 , B65D83/04 , B65D83/0409
摘要： Packaging for a pharmaceutical product and a method of validating pharmaceuticals is disclosed. The packaging comprising a cavity; and validation circuitry comprising: a sensor adapted to output a signal in response to detecting a vapour in the cavity; and a detection circuit adapted to output an indication when the signal indicates a predefined vapour signature.

5. 发明申请

WO2017216511A1 ESTIMATING A NUMBER OF OCCUPANTS IN A REGION 审中-公开
标题翻译：估算一个地区的一定数量的职业人员
公开(公告)号：WO2017216511A1
公开(公告)日：2017-12-21
申请号：PCT/GB2017/050978
申请日：2017-04-07
申请人： ARM LIMITED
发明人： RAYKOV, Yordan Petrov , ÖZER, Emre , DASIKA, Ganesh Suryanarayan
IPC分类号： G06Q10/00 , G06Q50/16
摘要： A method for estimating a number of occupants in a region comprises receiving a time series of sensor values detected over a period of time by a motion sensor sensing motion in the region. A spread parameter indicative of the spread of the sensor values is determined. The number of occupants in the region is estimated based on the spread parameter.
摘要翻译：用于估计区域中的乘员数量的方法包括接收由区域中的感测运动的运动传感器在一段时间内检测到的时间序列的传感器值。确定指示传感器值的扩展的扩展参数。该区域内的居住人数根据展布参数估算。

6. 发明申请

WO2007101969A1 ACCESSING A CACHE IN A DATA PROCESSING APPARATUS 审中-公开
标题翻译：在数据处理设备中访问缓存
公开(公告)号：WO2007101969A1
公开(公告)日：2007-09-13
申请号：PCT/GB2006/000795
申请日：2006-03-06
申请人： ARM LIMITED , FORD, Simon, Andrew , GHOSH, Mrinmoy , ÖZER, Emre , BILES, Stuart, David
发明人： FORD, Simon, Andrew , GHOSH, Mrinmoy , ÖZER, Emre , BILES, Stuart, David
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/1016 , G06F2212/6032 , Y02D10/13
摘要： A data processing apparatus is provided having processing logic for performing a sequence of operations, and a cache having a plurality of segments for storing data values for access by the processing logic. The processing logic is arranged, when access to a data value is required, to issue an access request specifying an address in memory associated with that data value, and the cache is responsive to the address to perform a lookup procedure during which it is determined whether the data value is stored in the cache. Indication logic is provided which, in response to an address portion of the address, provides for each of at least a subject of the segments an indication as to whether the data value is stored in that segment. The indication logic has guardian storage for storing guarding data, and hash logic for performing a hash operation on the address portion in order to reference the guarding data to determine each indication. Each indication indicates whether the data value is either definitely not stored in the associated segment or is potentially stored with the associated segment, and the cache is then operable to use the indications produced by the indication logic to affect the lookup procedure performed in respect of any segment whose associated indication indicates that the data value is definitely not stored in that segment. This technique has been found to provide a particularly power efficient mechanism for accessing the cache.
摘要翻译：提供了具有用于执行操作序列的处理逻辑的数据处理装置，以及具有多个段的高速缓存，用于存储由处理逻辑进行访问的数据值。当需要访问数据值时，处理逻辑被布置为发出指定与该数据值相关联的存储器中的地址的访问请求，并且高速缓存响应于地址以执行查找过程，在此期间确定是否确定是否数据值存储在缓存中。提供指示逻辑，响应于地址的地址部分，为段中的至少一个对象提供关于数据值是否存储在该段中的指示。指示逻辑具有用于存储保护数据的保护存储和用于对地址部分执行散列操作的散列逻辑，以引用保护数据来确定每个指示。每个指示指示数据值是否绝对不存储在相关联的段中或潜在地与相关联的段相关联，并且高速缓存然后可操作以使用由指示逻辑产生的指示来影响关于任何其相关联的指示表明数据值绝对不存储在该段中。已经发现这种技术提供了用于访问高速缓存的特别有效的机构。

7. 发明申请

WO2021038216A1 DATA PROCESSING 审中-公开
公开(公告)号：WO2021038216A1
公开(公告)日：2021-03-04
申请号：PCT/GB2020/052034
申请日：2020-08-24
申请人： ARM LIMITED
发明人： REYNOLDS, Charles Edward Michael , ÖZER, Emre
IPC分类号： G06F7/544
摘要： Data processing apparatus comprises binary neural network, BNN, circuitry to implement a BNN; the BNN circuitry comprising at least one instance of hidden layer circuitry responsive to trained one-bit weight values and input data values to generate a hidden layer output signal; in which: each input data value comprises a one-hot n-bit data value, where n is an integer greater than one, in which, for any input data value, only one bit of the given input data value has a first predetermined bit value and all other bits of that input data value have a second predetermined bit value complementary to the first predetermined bit value, the trained one-bit weight values comprise groups of n trained one-bit weight values, each group being associated with a respective input data value; the hidden layer circuitry is configured to generate the hidden layer output signal dependent upon an intermediate result of a selective inversion operation applied to each bit of a given input data value, the selective inversion operation being defined, as one of an inversion operation and a non-inversion operation, by a bit value of a respective one of the trained one-bit weight values of the group of trained one-bit weight values associated with the given input data value; the hidden layer circuitry comprises, for a group of trained one-bit weight values which all define a non-inversion operation, circuitry to generate a respective intermediate result as a first predetermined result value for the given input data value which is independent of the given input data value; and, for a group of trained one-bit weight values which all define an inversion operation, circuitry to generate a respective intermediate result as a second predetermined result value for the given input data value which is independent of the given input data value.

8. 发明申请

WO2020240149A1 SMART LABELS 审中-公开
公开(公告)号：WO2020240149A1
公开(公告)日：2020-12-03
申请号：PCT/GB2020/050618
申请日：2020-03-12
申请人： ARM LIMITED
发明人： ÖZER, Emre , SAVANTH, Parameshwarappa Anand Kumar , KUFEL, Jedrzej
IPC分类号： H02N2/18
摘要： Smart labels, methods of operating smart labels, and associated contexts in which such smart labels may be used are disclosed. The smart label, for use in conjunction with consumer product packaging, comprises an energy harvester to capture ambient energy to provide a source of electrical energy and electronic circuitry powered by the electrical energy. A fuse provides an electrical connection between the energy harvester and the electronic circuitry and destruction of the fuse permanently disconnects the energy harvester from the electronic circuitry. Unnecessary continued operation of the electronic circuitry powered by the energy harvester can therefore be prevented, for example when the consumer product packaging is disposed of or recycled, which may be an undesirable heat source. Smart labelling, and a connected network of smart bins which can read the smart labelling, may also be used to promote consumer recycling of consumer product packaging.

9. 发明申请

WO2020016550A1 MEMORY SCANNING OPERATION IN RESPONSE TO COMMON MODE FAULT SIGNAL 审中-公开
公开(公告)号：WO2020016550A1
公开(公告)日：2020-01-23
申请号：PCT/GB2019/051570
申请日：2019-06-06
申请人： ARM LIMITED
发明人： MERIAC, Milosch , ÖZER, Emre , ITURBE, Xabier , VENU, Balaji , DAS, Shidhartha
IPC分类号： G06F11/07 , G06F11/16
摘要： An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

10. 发明申请

WO2009106788A1 INTEGRATED CIRCUIT WITH ERROR REPAIR AND FAULT TOLERANCE 审中-公开
标题翻译：具有错误维修和故障保修的集成电路
公开(公告)号：WO2009106788A1
公开(公告)日：2009-09-03
申请号：PCT/GB2008/004301
申请日：2008-12-29
申请人： ARM LIMITED , DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
发明人： DAS, Shidhartha , BULL, David, Michael , ÖZER, Emre
IPC分类号： G01R31/3181 , G06F11/10
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.
摘要翻译：集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。控制参数取决于电路内执行的处理。例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

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