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1. 发明申请

WO2013177003A1 CONFORMAL SACRIFICIAL FILM BY LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION TECHNIQUE 审中-公开
标题翻译：低温化学气相沉积技术的合成薄膜
公开(公告)号：WO2013177003A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/041718
申请日：2013-05-17
申请人： APPLIED MATERIALS, INC. , XU, Jingjing , CRUZ, Joe Griffith , MANNA, Pramit , PADHI, Deenesh , KIM, Bok Hoen , CHIN, Barry L.
发明人： XU, Jingjing , CRUZ, Joe Griffith , MANNA, Pramit , PADHI, Deenesh , KIM, Bok Hoen , CHIN, Barry L.
IPC分类号： H01L21/312 , H01L21/311 , H01L21/205
CPC分类号： G03F7/167 , H01L21/02118 , H01L21/02277 , H01L21/0271
摘要： Methods and apparatus for forming a sacrificial during a novel process sequence of lithography and photoresist patterning are provided. In one embodiment, a method of processing a substrate having a resist material and an anti-reflective coating material thereon includes depositing an organic polymer layer over the surface of the substrate inside a process chamber using a CVD technique. The CVD technique includes flowing a monomer into a processing region of the process chamber, flowing an initiator into the processing region through one or more filament wires heated to a temperature between about 200C and about 450C, and forming the organic polymer layer. In addition, the organic polymer layer is ashable and can be removed from the surface of the substrate when the resist material is removed from the surface of the substrate.
摘要翻译：提供了在光刻和光致抗蚀剂图案化的新工艺序列期间形成牺牲的方法和装置。在一个实施例中，一种在其上处理具有抗蚀剂材料和抗反射涂层材料的衬底的方法包括使用CVD技术在处理室内的衬底的表面上沉积有机聚合物层。 CVD技术包括使单体流入处理室的处理区域，通过加热到约200℃至约450℃之间的温度的一根或多根细丝丝将引发剂流入加工区域，并形成有机聚合物层。另外，当从基板的表面去除抗蚀剂材料时，有机聚合物层是可灰化的，并且可以从基板的表面去除。

2. 发明申请

WO2011152966A2 CHEMICAL PLANARIZATION OF COPPER WAFER POLISHING 审中-公开
标题翻译：铜波抛光的化学平面化
公开(公告)号：WO2011152966A2
公开(公告)日：2011-12-08
申请号：PCT/US2011/036019
申请日：2011-05-11
申请人： APPLIED MATERIALS, INC. , WANG, You , TU, Wen-Chiang , LIU, Feng Q. , WANG, Yuchun , KARUPPIAH, Lakshmanan , MC CLINTOCK, William H. , CHIN, Barry L.
发明人： WANG, You , TU, Wen-Chiang , LIU, Feng Q. , WANG, Yuchun , KARUPPIAH, Lakshmanan , MC CLINTOCK, William H. , CHIN, Barry L.
IPC分类号： H01L21/304
CPC分类号： H01L21/3212 , B24B37/044 , C09G1/04 , H01L21/7684
摘要： Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarzing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.
摘要翻译：本文所述的实施例涉及从衬底去除材料。更具体地，本文所述的实施例涉及通过化学机械抛光工艺抛光或平面化衬底。在一个实施例中，提供了基板的化学机械抛光（CMP）的方法。该方法包括将其上形成有导电材料层的基板暴露于包含磷酸，一种或多种螯合剂，一种或多种腐蚀抑制剂和一种或多种氧化剂的抛光溶液，在导电材料层上形成钝化层，提供衬底和抛光垫之间的相对运动，并移除钝化层的至少一部分以暴露下面的导电材料层的一部分，以及去除暴露的导电材料层的一部分。

3. 发明申请

WO2002073689A2 INTEGRATED BARRIER LAYER STRUCTURE FOR COPPER CONTACT LEVEL METALLIZATION 审中-公开
标题翻译：用于铜接触层级金属化的集成阻挡层结构
公开(公告)号：WO2002073689A2
公开(公告)日：2002-09-19
申请号：PCT/US2002/007276
申请日：2002-03-08
申请人： APPLIED MATERIALS, INC.
发明人： CHIANG, Tony , DING, Peijun , CHIN, Barry L.
IPC分类号： H01L21/768
CPC分类号： H01L21/76855 , H01L21/2855 , H01L21/28556 , H01L21/76843
摘要： A method for forming an integrated barrier layer structure that is compatible with copper (Cu) metallization schemes for integrated circuit fabrication is disclosed. In one aspect, an integrated circuit is metallized by forming an integrated barrier layer structure on a silicon substrate followed by deposition of one or more copper (Cu) layers. The integrated barrier layer structure includes one or more barrier layers selected from tantalum (Ta), tantalum nitride (TaN x ), tungsten (W), and tungsten nitride (WN x ) conformably deposited on the silicon substrate. After the one or more barrier layers are deposited on the silicon substrate, the silicon substrate is heated to form a silicide layer at the interface between the silicon substrate and the barrier layers.
摘要翻译：公开了一种与集成电路制造用铜（Cu）金属化方案兼容的集成阻挡层结构的形成方法。在一个方面中，通过在硅衬底上形成集成的阻挡层结构，然后沉积一个或多个铜（Cu）层，从而对集成电路进行金属化。集成阻挡层结构包括从硅（Ta），氮化钽（TaNx），钨（W）和钨氮化物（WNx）中选择的一个或多个势垒层，其顺应地沉积在硅衬底上。在一个或多个阻挡层沉积在硅衬底上之后，硅衬底被加热以在硅衬底和阻挡层之间的界面处形成硅化物层。

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