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1. 发明申请

WO2011017256A2 EQUALIZATION FOR OFDM COMMUNICATION 审中-公开
标题翻译： OFDM通信的均衡
公开(公告)号：WO2011017256A2
公开(公告)日：2011-02-10
申请号：PCT/US2010044098
申请日：2010-08-02
申请人： ANALOG DEVICES INC , PRIMO HAIM , STEIN YOSEF , AN WEI
发明人： PRIMO HAIM , STEIN YOSEF , AN WEI
IPC分类号： H04L25/02
CPC分类号： H04L25/0212 , H04L25/0218 , H04L25/03159 , H04L2025/03414 , H04L2025/03535 , H04L2025/03726
摘要： The problem of inefficient channel impulse-response processing is addressed by processing different parts of a channel impulse response to accurately locate channel taps, and to generate more than one set of equalization coefficients. This allows the most-suited equalization coefficient to be selected based on a selection criterion.
摘要翻译：通过处理信道脉冲响应的不同部分来精确地定位信道抽头并产生多于一组的均衡系数来解决低效率信道脉冲响应处理的问题。这允许基于选择标准来选择最合适的均衡系数。

2. 发明申请

WO2008048630A2 IMPROVED CHANNEL ESTIMATION SYSTEM AND METHOD 审中-公开
标题翻译：改进的信道估计系统和方法
公开(公告)号：WO2008048630A2
公开(公告)日：2008-04-24
申请号：PCT/US2007022129
申请日：2007-10-17
申请人： ANALOG DEVICES INC , PRIMO HAIM , STEIN YOSEF , AN WEI
发明人： PRIMO HAIM , STEIN YOSEF , AN WEI
IPC分类号： H04L27/00
CPC分类号： H04L25/03038 , H04B17/345 , H04B17/364 , H04L25/0218 , H04L25/0228 , H04L25/025 , H04L25/03159 , H04L27/2647 , H04L2025/03414 , H04L2025/03783
摘要： Channel estimation for high mobility OFDM channels is achieved by identifying a set of channel path delays from an OFDM symbol stream including carrier data, inter-channel interference noise and channel noise; determining the average channel impulse response for the identified set of channel path delays in each symbol; storing the average channel impulse responses for the identified channel path delays; generating a path delay curvature for each channel path delay in each symbol based on stored average channel impulse responses for the identified channel path delays; estimating the carrier data in the symbols in the OFDM symbol stream in the presence of inter-channel interference noise and channel noise from the OFDM symbol steam and the average impulse responses for the identified channel path delays; reconstructing the inter-channel interference noise in response to the path delay curvature, the identified set of channel path delays and estimated carrier data; and subtracting the reconstructed inter-channel interference noise from the OFDM symbol stream to produce a symbol stream of carrier data and channel noise with suppressed inter-channel interference noise.
摘要翻译：高移动性OFDM信道的信道估计通过从包括载波数据，信道间干扰噪声和信道噪声的OFDM符号流中识别一组信道路径延迟来实现; 确定每个符号中识别的一组信道路径延迟的平均信道脉冲响应; 存储针对所识别的信道路径延迟的平均信道脉冲响应; 基于存储的用于所识别的信道路径延迟的平均信道脉冲响应，为每个符号中的每个信道路径延迟生成路径延迟曲率; 在存在来自OFDM符号流的信道间干扰噪声和信道噪声以及所识别的信道路径延迟的平均脉冲响应的情况下，估计OFDM符号流中的符号中的载波数据; 响应于路径延迟曲率，所识别的一组信道路径延迟和估计的载波数据来重构信道间干扰噪声; 并从OFDM符号流中减去重构的信道间干扰噪声，以产生具有抑制的信道间干扰噪声的载波数据和信道噪声的符号流。

3. 发明申请

WO2004092873A3 GALOIS FIELD LINEAR TRANSFORMER TRELLIS SYSTEM 审中-公开
标题翻译： GALOIS现场线性变压器TRELLIS系统
公开(公告)号：WO2004092873A3
公开(公告)日：2006-08-24
申请号：PCT/US2004010656
申请日：2004-04-07
申请人： ANALOG DEVICES INC , STEIN YOSEF , PRIMO HAIM
发明人： STEIN YOSEF , PRIMO HAIM
IPC分类号： G06F15/00 , G06F20060101 , G06F9/30 , G06G7/16 , H03M13/23 , H04L1/00
CPC分类号： H03M13/235 , H03M13/6516 , H03M13/6561 , H03M13/6575 , H04L1/0041 , H04L1/0059
摘要： A galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.
摘要翻译：伽罗瓦域线性变压器网格系统包括伽罗瓦域线性变压器矩阵; 输入选择电路，用于向矩阵提供矩阵中的一个或多个格状比特流中的多个输入比特和矩阵的网格状态输出，以及用于配置矩阵以执行所述矩阵的多周期伽罗瓦域变换的可编程存储装置或更多的网格位流和网格状态输出，以在单个周期中提供多个网格输出通道符号和新的网格状态输出。

4. 发明申请

WO2008039321A3 ITERATIVE PROCESS WITH ROTATED ARCHITECTURE FOR REDUCED PIPELINE DEPENDENCY 审中-公开
标题翻译：用于减少管道依赖的旋转结构的迭代过程
公开(公告)号：WO2008039321A3
公开(公告)日：2008-10-30
申请号：PCT/US2007020145
申请日：2007-09-18
申请人： ANALOG DEVICES INC , WILSON JAMES , KABLOTSKY JOSHUA , STEIN YOSEF , MAYER CHRISTOPHER M
发明人： WILSON JAMES , KABLOTSKY JOSHUA , STEIN YOSEF , MAYER CHRISTOPHER M
IPC分类号： G06F7/38
CPC分类号： H04N19/436 , H04N19/13 , H04N19/61
摘要： In a pipeline machine where, in an iterative process, one or more subsequent functions employ one or more parameters determined by one or more antecedent functions and the one or more subsequent functions generate one or more parameters for the one or more antecedent functions, pipeline dependency is reduced by advancing or rotating the iterative process by preliminarily providing to the subsequent function the next one or more parameters on which it is dependent and thereafter: generating by the subsequent function, in response to the one or more parameters on which is it dependent, the next one or more parameters required by the one or more antecedent functions and then, generating by the one or more antecedent functions, in response to the one or more parameters required by the one or more antecedent functions, the next one or more parameters for input to the subsequent function for the next iteration.
摘要翻译：在管线机器中，其中在迭代过程中，一个或多个后续功能采用由一个或多个先行函数确定的一个或多个参数，并且所述一个或多个后续函数为一个或多个先行函数生成一个或多个参数，流水线依赖通过预先向随后的功能提供下一个或多个依赖于其的参数，然后：通过随后的功能生成响应于依赖于其的一个或多个参数，推进或旋转迭代过程，一个或多个先行函数所需的下一个或多个参数，然后响应于一个或多个先行函数所要求的一个或多个参数，由一个或多个先行函数生成下一个或多个参数，用于输入下一次迭代的后续功能。

5. 发明申请

WO2008051350A2 METHOD AND APPARATUS FOR MAPPING THE PRIMARY OPERATIONAL SEQUENCES OF AN ALGORITHM IN A COMPUTE UNIT HAVING AN INTERNAL RANDOM ACCESS MEMORY 审中-公开
标题翻译：用于映射具有内部随机访问存储器的计算机单元中的算法的主要操作序列的方法和装置
公开(公告)号：WO2008051350A2
公开(公告)日：2008-05-02
申请号：PCT/US2007020971
申请日：2007-09-28
申请人： ANALOG DEVICES INC , STEIN YOSEF , MALEPATI HAZARATHAIAH , YUKNA GREGORY M
发明人： STEIN YOSEF , MALEPATI HAZARATHAIAH , YUKNA GREGORY M
IPC分类号： G06F7/38
CPC分类号： H03M7/4006 , H03M7/42 , H04N19/42 , H04N19/91
摘要： A method and apparatus for direct mapping in a compute unit having an internal random access memory the primary operational sequences of an algorithm to related function including storing in an internal random access memory at least one predetermined direct mapped function value for each primary operational sequence of an algorithm; holding in an input data register the address in the random access memory of at least one mapped function value for a selected primary operational sequence of the algorithm and holding in an output register the at least one mapped function value for the selected primary operational sequence of the algorithm read out of the random access memory.
摘要翻译：一种用于在具有内部随机存取存储器的计算单元中直接映射的方法和装置，所述算法的主要操作序列与相关功能包括在内部随机存取存储器中存储至少一个预定的直接映射函数值，算法; 在输入数据寄存器中保存所述算法的所选主要操作序列的至少一个映射函数值的随机存取存储器中的地址，并且在输出寄存器中保存用于所选择的主操作序列的至少一个映射函数值算法读出随机存取存储器。

6. 发明申请

WO2007015776A2 INSTRUCTION BASED PARALLEL MEDIAN FILTERING PROCESSOR AND METHOD 审中-公开
标题翻译：基于指令的并行中值滤波处理器和方法
公开(公告)号：WO2007015776A2
公开(公告)日：2007-02-08
申请号：PCT/US2006027532
申请日：2006-07-18
申请人： ANALOG DEVICES INC , WILSON JAMES , KABLOTSKY JOSHUA A , STEIN YOSEF , YUKNA GREGORY M
发明人： WILSON JAMES , KABLOTSKY JOSHUA A , STEIN YOSEF , YUKNA GREGORY M
IPC分类号： G06F17/10
CPC分类号： H03H17/0263 , G06F7/22 , G06F7/544
摘要： An instruction based parallel median filtering processor and method sorts in parallel each combination of pairs of inputs into greater and lesser values; determines from that sorting the minimum, maximum and median filter values of the inputs; and applies at least one instruction for enabling indication of at least one of the maximum, minimum, median filter values.
摘要翻译：基于指令的并行中值滤波处理器和方法将输入对的每个组合并行分类为更大和更小的值; 根据该排序确定输入的最小值，最大值和中值滤波值; 并且应用至少一个指令来启用指示最大值，最小值，中值滤波值中的至少一个。

7. 发明申请

WO2008130544A3 PROGRAMMABLE COMPUTE SYSTEM FOR EXECUTING AN H.264 BINARY DECODE SYMBOL INSTRUCTION 审中-公开
标题翻译： H.264可编程序编译器系统，用于执行H.264二进制解码符号指令
公开(公告)号：WO2008130544A3
公开(公告)日：2009-01-15
申请号：PCT/US2008004852
申请日：2008-04-15
申请人： ANALOG DEVICES INC , WILSON JAMES , KABLOTSKY JOSHUA , STEIN YOSEF , MAYER CHRISTOPHER M
发明人： WILSON JAMES , KABLOTSKY JOSHUA , STEIN YOSEF , MAYER CHRISTOPHER M
IPC分类号： H03M7/00
CPC分类号： H03M7/4006
摘要： A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.
摘要翻译：一种用于执行h.264二进制解码符号指令的计算系统，包括具有范围归一化电路和rLPS更新电路的第一计算单元，并且响应于当前的rLPS，范围，值和当前上下文以第一模式操作以产生下一个标准化范围和下一个rLPS为当前上下文; 第二计算单元，包括响应于当前rLPS，范围值和当前上下文的值更新电路，上下文更新电路和值归一化电路，以获得输出位，归一化值和更新的当前上下文; 以及第三计算单元或所述第一计算单元，其以第二模式操作，包括响应于rLPS范围，值和下一个上下文的范围电路和下一个上下文rLPS电路，以获得下一个上下文rLPS值。

8. 发明申请

WO2007050361A3 IMPROVED PIPELINED DIGITAL SIGNAL PROCESSOR 审中-公开
标题翻译：改进的流水线数字信号处理器
公开(公告)号：WO2007050361A3
公开(公告)日：2007-12-13
申请号：PCT/US2006040510
申请日：2006-10-17
申请人： ANALOG DEVICES INC , WILSON JAMES , KABLOTSKY JOSHUA A , STEIN YOSEF , PRENDERGAST COLM J , YUKNA GREGORY M , MAYER CHRISTOPHER M
发明人： WILSON JAMES , KABLOTSKY JOSHUA A , STEIN YOSEF , PRENDERGAST COLM J , YUKNA GREGORY M , MAYER CHRISTOPHER M
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F9/3001 , G06F9/345 , G06F9/3885
摘要： Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.
摘要翻译：响应于算法的指令，通过计算计算单元中的结果可以实现减少处理器中的计算单元和地址单元之间的流水线延迟; 在计算单元中的局部随机存取存储器阵列中存储与算法的预定指令集的计算结果有关的预定函数集合; 并在计算单元内提供计算结果与相关函数的直接映射。

9. 发明申请

WO2005029755A3 ADVANCED ENCRYPTION STANDARD (AES) ENGINE WITH REAL TIME S-BOX GENERATION 审中-公开
标题翻译：高级加密标准（AES）发动机与实时S-BOX生成
公开(公告)号：WO2005029755A3
公开(公告)日：2006-01-26
申请号：PCT/US2004030742
申请日：2004-09-17
申请人： ANALOG DEVICES INC , STEIN YOSEF , KABLOTSKY JOSHUA A
发明人： STEIN YOSEF , KABLOTSKY JOSHUA A
IPC分类号： H04L9/06 , H04K1/04
CPC分类号： H04L9/0631 , H04L2209/12
摘要： An advanced encryption standard (AES) engine with real time S-box (18) generation includes a Galois field multiplier system in a first mode responsive to a first data block (16) for generating an AES selection (S-box) function by executing the multiplicative increase in GF
摘要翻译：具有实时S盒（18）生成的高级加密标准（AES）引擎包括响应于第一数据块（16）的第一模式的伽罗瓦域乘法器系统，用于通过执行AES生成AES选择（S盒）功能 GF

10. 发明申请

WO2004105260A3 COMPOUND GALOIS FIELD ENGINE AND GALOIS FIELD DIVIDER AND SQUARE ROOT ENGINE AND METHOD 审中-公开
标题翻译：化合物GALOIS现场发动机和GALOIS现场分路器和平方根发动机和方法
公开(公告)号：WO2004105260A3
公开(公告)日：2005-07-07
申请号：PCT/US2004009536
申请日：2004-03-29
申请人： ANALOG DEVICES INC , STEIN YOSEF , KABLOTSKY JOSHUA A
发明人： STEIN YOSEF , KABLOTSKY JOSHUA A
IPC分类号： G06F7/00 , G06F7/38 , G06F7/552 , G06F7/72 , G06F15/00 , H04B20060101
CPC分类号： G06F7/726 , G06F7/552 , G06F2207/5523
摘要： A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in a Galois field reciprocal generator a first Galois field element by a first element of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m-2 times where m is the degree of the Galois field to obtain the reciprocal of the first Galois field element, and multiplying in the Galois field reciprocal engine the reciprocal of the first Galois field element by a second Galois field element for predicting the modulo remainder of the polynomial product for an irreducible polynomial to obtain the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform; Galois field square root is achieved by inputting a Galois field element to a Galois field square root generator to obtain an output which is squared in the Galois field square root generator to predict the modulo remainder of the square of the polynomial product of an irreducible polynomial m-1 times where m is the degree of the Galois field to obtain the square root of the Galois field to obtain the square root of the Galois field element in (m-1) cycles.
摘要翻译：伽罗瓦域除法器引擎和方法将1和第一伽罗瓦域元素输入到伽罗瓦域互逆发生器以获得输出，在伽罗瓦域互逆发生器中乘以伽罗瓦域互逆发生器的第一元素的第一伽罗瓦域元件，预测不可约多项式m-2倍的多项式积的平方的模余数，其中m是伽罗瓦域获得第一伽罗瓦域元的倒数的程度，并且在伽罗瓦域互逆引擎中乘以第一伽罗瓦域元素，用于预测用于不可约多项式的多项式积的模余数，以获得以m个周期的两个伽罗瓦域元素的商; 在更广泛的意义上，本发明包括用于在一系列多项式输入上执行伽罗瓦域线性变换的连续性以获得最终输出的复合Galois场引擎，其中除第一个之外的每个输入是先前伽罗瓦域线性变换的输出; 伽罗瓦域平方根通过将伽罗瓦域元素输入到伽罗瓦域平方根生成器来获得在伽罗瓦域平方根生成器中平方的输出，以预测不可约多项式m的多项式积的平方的模余数 -1次，其中m是伽罗瓦域的程度以获得伽罗瓦域的平方根，以获得（m-1）个周期中伽罗瓦域元素的平方根。

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