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1. 发明申请

WO1991011863A1 SIGMA DELTA MODULATOR 审中-公开
标题翻译： SIGMA DELTA调制器
公开(公告)号：WO1991011863A1
公开(公告)日：1991-08-08
申请号：PCT/US1991000686
申请日：1991-01-31
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , FERGUSON, Paul, F., Jr. , GANESAN, Apparajan , ADAMS, Robert, W.
IPC分类号： H03M03/02
CPC分类号： H03G3/02 , H03M3/43 , H03M3/446 , H03M3/45 , H03M3/454 , H03M7/3028 , H03M7/3035 , H03M7/304
摘要： A separate filter circuit (1512, 1522, 1532) is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.
摘要翻译：在常规Σ-Δ调制器的反馈路径中的D / A转换器和求和结点之间插入单独的滤波器电路（1512,1522,1532）。该附加滤波器允许独立于正向信号传递函数来控制量化噪声传递函数谱。通过适当调整传递函数，可以构建第三个或更高阶的调制器，而不会产生不稳定的发展。调制器也可以构造为完全数字电路，并用作数字数/模转换器中的噪声整形电路。

2. 发明申请

WO1995002923A1 METHOD AND APPARATUS FOR CALIBRATING A GAIN CONTROL CIRCUIT 审中-公开
标题翻译：用于校准增益控制电路的方法和装置
公开(公告)号：WO1995002923A1
公开(公告)日：1995-01-26
申请号：PCT/US1994007334
申请日：1994-06-29
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , MUECK, Michael , FERGUSON, Paul, F., Jr.
IPC分类号： H03G01/04
CPC分类号： H03G1/04 , H03M1/1019 , H03M1/66 , H03M3/38 , H03M3/51
摘要： A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.
摘要翻译：系统包括数模转换器电路和校准电路。数模转换器电路包括提供音量调节的增益控制电路。该系统包括校准模式和正常操作模式。在校准期间，与增益控制电路相关联的校正值由校准电路测量并存储。在正常操作期间，将存储的校正值与其提供给DAC电路之前的输入组合，使得对于预定的中间码的输入，期望的系统输出保持恒定，尽管增益控制的音量设置有任何改变电路。

3. 发明申请

WO1994023494A1 DOUBLE SAMPLED BIQUAD SWITCHED CAPACITOR FILTER 审中-公开
标题翻译：双重采样生物量开关电容滤波器
公开(公告)号：WO1994023494A1
公开(公告)日：1994-10-13
申请号：PCT/US1994003785
申请日：1994-04-06
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , KWAN, Tom, W. , FERGUSON, Paul, F., Jr. , LEE, Wai, L.
IPC分类号： H03H19/00
CPC分类号： H03H19/004
摘要： A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.
摘要翻译：双倍开关电容滤波器优选地用作Σ-Δ数模转换器中的输出滤波器。开关电容滤波器使用交叉耦合开关电容器电路，其在时钟的两相上向电容器递送电荷。结果，电容器的尺寸可以减少2倍，同时提供与单个采样电路相同的电荷。通过在滤波器中的任何地方使用交叉耦合开关电路，电容器失配的灵敏度大大降低。施加到滤波器的级的时钟相位交替，使得在包含两个滤波器级的每个回路周围有一个时钟周期延迟，从而确保滤波器的稳定性。

4. 发明申请

WO2003103150A1 OFFSET CALIBRATION SYSTEM 审中-公开
标题翻译：偏移校准系统
公开(公告)号：WO2003103150A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/011853
申请日：2003-04-17
申请人： ANALOG DEVICES, INC
发明人： GEALOW, Jeffrey , C. , BARBER, Thomas, J., Jr. , FERGUSON, Paul, F., Jr. , HAURIE, Xavier, S.
IPC分类号： H03M1/00
CPC分类号： H03M1/1019 , H03M1/02
摘要： An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.
摘要翻译：偏移校准系统包括具有第一满量程范围的模数转换器，具有第一偏移补偿电路; 具有第二满量程范围的数模转换器，具有第二偏移补偿电路; 所述数模转换器在所述数模转换器的校准期间将其输出连接到所述模数转换器的输入; 以及范围调整电路，用于累积预定数量的模拟数字输出值，并以与模数转换器最低有效位相对应的电压的比率将累加值除以2的预选功率，对应于数字到模拟转换器的最低有效位。

5. 发明申请

WO1996031944A1 IN-PHASE AND QUADRATURE SAMPLING CIRCUIT 审中-公开
标题翻译：相间和正交采样电路
公开(公告)号：WO1996031944A1
公开(公告)日：1996-10-10
申请号：PCT/US1996004685
申请日：1996-04-05
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , LEE, Wai, L. , GRANT, Norman, D. , FERGUSON, Paul, F., Jr.
IPC分类号： H03D07/16
CPC分类号： H03D7/165
摘要： A circuit that provides samples of in-phase and quadrature componenents of an input waveform includes an oversampling sigma-delta ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.
摘要翻译：提供输入波形的同相和正交分量样本的电路包括过采样Σ-ΔADC，其接收输入波形，并以过采样速率将输入波形转换为数字采样。耦合到ADC的第一个数字滤波器从ADC接收数字采样，并提供输入波形的同相分量采样。耦合到ADC的第二个数字滤波器从ADC接收数字采样，并提供输入波形的正交分量采样。

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