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1. 发明申请

WO2006004166A8 DATA PROCESSING UNIT AND COMPATIBLE PROCESSOR 审中-公开
公开(公告)号：WO2006004166A8
公开(公告)日：2006-01-12
申请号：PCT/JP2005/012516
申请日：2005-06-30
申请人： SSD COMPANY LIMITED , KATO, Shuhei , SANO, Koichi , USAMI, Koichi
发明人： KATO, Shuhei , SANO, Koichi , USAMI, Koichi
IPC分类号： G06F13/362
摘要： A processor maintaining backward compatibility with a previous generation processor is provided. When an operation is performed in a current generation processor 100 for writing a value to an address, which is the same address as assigned to a zeroth area access cycle number register of a previous generation processor 500, the same value is written to a zeroth area random access cycle number register 170, and a zeroth area page size register 190 is set to '0' (page size = 0 byte) such that the page mode is disabled. On the other hand, when an operation is executed by the current generation processor 100 for writing a value to an address, which is the same address as assigned to a first and a second area access cycle number register of the previous generation processor 500, the same value is written to both a first area random access cycle number register 171 and a second area random access cycle number register 172, and a first area page size register 191 and a second area page size register 192 are set to '0' such that the page mode is disabled.

2. 发明申请

WO2006004166A1 DATA PROCESSING UNIT AND COMPATIBLE PROCESSOR 审中-公开
标题翻译：数据处理单元和兼容处理器
公开(公告)号：WO2006004166A1
公开(公告)日：2006-01-12
申请号：PCT/JP2005012516
申请日：2005-06-30
申请人： SSD CO LTD , KATO SHUHEI , SANO KOICHI , USAMI KOICHI
发明人： KATO SHUHEI , SANO KOICHI , USAMI KOICHI
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , G06F9/355 , G06F12/0623
摘要： A processor maintaining backward compatibility with a previous generation processor is provided. When an operation is performed in a current generation processor 100 for writing a value to an address, which is the same address as assigned to a zeroth area access cycle number register of a previous generation processor 500, the same value is written to a zeroth area random access cycle number register 170, and a zeroth area page size register 190 is set to "0" (page size = 0 byte) such that the page mode is disabled. On the other hand, when an operation is executed by the current generation processor 100 for writing a value to an address, which is the same address as assigned to a first and a second area access cycle number register of the previous generation processor 500, the same value is written to both a first area random access cycle number register 171 and a second area random access cycle number register 172, and a first area page size register 191 and a second area page size register 192 are set to "0" such that the page mode is disabled.
摘要翻译：提供了与上一代处理器保持向后兼容性的处理器。当在当前一代处理器100中执行一个操作，用于向与前一代处理器500的第零区域访问周期数寄存器分配的地址相同的地址写入值时，将相同的值写入零区域随机访问周期数寄存器170和零区域页面大小寄存器190设置为“0”（页大小= 0字节），使得页面模式被禁用。另一方面，当由当前一代处理器100执行一个操作以将值写入与分配给上一代处理器500的第一和第二区域访问周期数寄存器的地址相同的地址时，相同的值被写入第一区随机存取周期数寄存器171和第二区随机存取周期数寄存器172以及第一区域页大小寄存器191和第二区页大小寄存器192被设置为“0”，使得页面模式被禁用。

3. 发明申请

WO2006001506A1 IMAGE MIXING APPARATUS AND PIXEL MIXER 审中-公开
标题翻译：图像混合装置和像素混合器
公开(公告)号：WO2006001506A1
公开(公告)日：2006-01-05
申请号：PCT/JP2005/012147
申请日：2005-06-24
申请人： SSD COMPANY LIMITED , KATO, Shuhei , SANO, Koichi , USAMI, Koichi
发明人： KATO, Shuhei , SANO, Koichi , USAMI, Koichi
IPC分类号： G06T3/00
CPC分类号： G09G5/395 , G09G5/001 , G09G2340/10 , G09G2340/12 , H04N1/387 , H04N5/265
摘要： An image mixing apparatus and a pixel mixer capable of mixing image data items having different pixel resolutions, and mixing image data items in an arbitrary display priority, irrespective of the order of mixing, even if the order of mixing is determined in advance is provided. Of two pixel data items having depth values "Zc" and "Zb", one pixel data item having the depth value indicating that the pixel is located in a foreground position is selected by a pixel selection determination circuit 110. However, if a pixel data item has a hue indicating that the pixel is transparent, such a pixel data item is not selected but another pixel data item is selected instead. Multiplexers 112 to 116 output a pixel data item (hue “Hm”/color saturation “Sm”/brightness “Lm”) which is selected by the pixel selection determination circuit 110. Since pixel data items are input to the multiplexer 112 to 116 at different output rates, it is possible to mix images having different pixel resolutions.
摘要翻译：提供了即使预先确定混合顺序，也可以混合能够混合具有不同像素分辨率的图像数据项的图像混合装置和像素混合器，并且混合任意显示优先级的图像数据项，而与混合顺序无关。在具有深度值“Zc”和“Zb”的两个像素数据项中，通过像素选择确定电路110选择具有指示像素位于前景位置的深度值的一个像素数据项。然而，如果像素数据项目具有指示像素是透明的色调，这样的像素数据项目不被选择，而是选择另一个像素数据项目。复用器112至116输出由像素选择确定电路110选择的像素数据项（色调“Hm”/色彩饱和度“Sm”/亮度“Lm”）。由于像素数据项被输入到多路复用器112至116 不同的输出速率，可以混合具有不同像素分辨率的图像。

4. 发明申请

WO2005119465A1 DATA PROCESSING UNIT AND BUS ARBITRATION UNIT 审中-公开
标题翻译：数据处理单元和总线仲裁单元
公开(公告)号：WO2005119465A1
公开(公告)日：2005-12-15
申请号：PCT/JP2005/010209
申请日：2005-05-27
申请人： SSD COMPANY LIMITED , KATO, Shuhei , SANO, Koichi , USAMI, Koichi
发明人： KATO, Shuhei , SANO, Koichi , USAMI, Koichi
IPC分类号： G06F13/362
CPC分类号： G06F13/364
摘要： An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal "CDSZ") indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.
摘要翻译：描述了一种有效的总线仲裁单元，其中可以尽可能地减少等待时间，直到总线主机获得总线所有权并提高总线的操作速率，同时提高数据传输的吞吐量。总线主机发出指示要读取或写入的数据大小的大小信号（例如，信号“CDSZ”）。状态机155向总线主机授予与大小信号相对应的总线周期的总线所有权，以使得总线主机能够连续地读取或写入数据。对于与总线主机所要求的大小相对应的每个系列总线，执行一次仲裁。由于由总线主机发出的尺寸信号作为指示数据传输所需和足够尺寸的尺寸信号，所以状态机155可以设置最佳的总线周期数。

5. 发明申请

WO2005116982A1 DATA PROCESSING UNIT, DRAWING APPARATUS AND PIXEL PACKER 审中-公开
标题翻译：数据处理单元，绘图设备和像素包装机
公开(公告)号：WO2005116982A1
公开(公告)日：2005-12-08
申请号：PCT/JP2005/009702
申请日：2005-05-20
申请人： SSD COMPANY LIMITED , KATO, Shuhei , SANO, Koichi , USAMI, Koichi
发明人： KATO, Shuhei , SANO, Koichi , USAMI, Koichi
IPC分类号： G09G5/393
CPC分类号： G06T11/40 , G06F12/0875 , G06T1/60 , G09G5/001 , G09G5/393 , G09G2360/121
摘要： A data processing unit for performing a high speed drawing operation of arbitrary patterns even in individual pixels is provided. It is assumed that the color mode is set to 3 bits per pixel. A pixel "N" is written to a drawing position designated by a byte address [29:3] and a bit address [2:0]. The subsequent pixel "N + 1" is written immediately after the pixel "N". The next subsequent pixel "N + 2" is written immediately after the pixel "N + 1" to span the adjacent bytes. Thereby, the pixel data is continuously stored within each byte and across the boundary between bytes with no space. In this case, the operation of writing pixel data, i.e., the drawing is performed not in words or bytes but in pixels. In addition to this, high speed drawing is possible by the use of a caching system.
摘要翻译：提供了即使在各个像素中执行任意图案的高速绘图操作的数据处理单元。假设颜色模式被设置为每像素3位。像素“N”被写入由字节地址[29：3]指定的绘图位置和位地址[2：0]。随后的像素“N + 1”被立即写入像素“N”之后。紧接在像素“N + 1”之后写入下一个后续像素“N + 2”以跨越相邻字节。由此，像素数据被连续地存储在每个字节之间并跨越不具有空格的字节之间的边界。在这种情况下，写入像素数据（即，绘制）的操作不以字或字节执行，而是以像素执行。除此之外，通过使用缓存系统可以实现高速绘图。

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