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1. 发明申请

WO2005038921A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：WO2005038921A1
公开(公告)日：2005-04-28
申请号：PCT/JP2004/015328
申请日：2004-10-08
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , TAKI, Masato , TOJIMA, Hideki
发明人： TAKI, Masato , TOJIMA, Hideki
IPC分类号： H01L27/06
CPC分类号： H01L29/7816 , H01L27/092 , H01L29/0615 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/7824 , H01L29/7835
摘要： A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.
摘要翻译：半导体装置（100）包括低电位基准电路区域（1）和高电位基准电路区域（2），高电位基准电路区域（2）由高耐压分离区域（3）包围。通过形成在高耐压分离区域（3）的外周的沟槽（4），低电位基准电路区域（1）和高电位基准电路区域（2）彼此分离。此外，沟槽（4）填充有绝缘材料，并使低电位参考电路区域（1）和高电位参考电路区域（2）绝缘。高耐压分离区域（3）由沟槽（4）分隔开，在分隔位置设有高耐压NMOS（5）或高耐压PMOS（6）。

2. 发明申请

WO2007072655A2 SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2007072655A2
公开(公告)日：2007-06-28
申请号：PCT/JP2006323513
申请日：2006-11-17
申请人： TOYOTA MOTOR CO LTD , TAKI MASATO , KAWAKAMI MASAHIRO , HAYAKAWA KIYOHARU , ISHIKO MASAYASU
发明人： TAKI MASATO , KAWAKAMI MASAHIRO , HAYAKAWA KIYOHARU , ISHIKO MASAYASU
IPC分类号： H01L29/78 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/861
CPC分类号： H01L29/8611 , H01L21/266 , H01L29/0634 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1608 , H01L29/20 , H01L29/24 , H01L29/402 , H01L29/66128 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835 , H01L29/78624
摘要： A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.
摘要翻译：二极管10包括层叠有半导体衬底20，绝缘体膜30和半导体层40的SOI衬底。在半导体中形成底部半导体区域60，中间半导体区域53和表面半导体区域54 底部半导体区域60包括高浓度的n型杂质。中间半导体区域53包括低浓度的n型杂质。表面半导体区域54包括p型杂质。

3. 发明申请

WO2007072655A3 LATERAL SOI SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：WO2007072655A3
公开(公告)日：2007-06-28
申请号：PCT/JP2006/323513
申请日：2006-11-17
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , TAKI, Masato , KAWAKAMI, Masahiro , HAYAKAWA, Kiyoharu , ISHIKO, Masayasu
发明人： TAKI, Masato , KAWAKAMI, Masahiro , HAYAKAWA, Kiyoharu , ISHIKO, Masayasu
IPC分类号： H01L29/78 , H01L29/861 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/22 , H01L29/24 , H01L29/20 , H01L29/10 , H01L29/786
摘要： A lateral diode (10) comprises an SOI substrate in which are stacked a semiconductor substrate (20), an insulator film (30), and a semiconductor layer (40). A bottom semiconductor region (60), an intermediate semiconductor region (53), and a surface semiconductor region (54) are formed in the semiconductor layer (40). The bottom semiconductor region (60) includes a high concentration of n-type impurity. The intermediate semiconductor region (53) includes a low concentration of n-type impurity. The surface semiconductor region (54) includes p-type impurity. LDMOS transistors are also disclosed.

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