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1. 发明申请

WO1997047089A1 PHASE LOCKED LOOP CIRCUIT 审中-公开
标题翻译：相位锁定环路
公开(公告)号：WO1997047089A1
公开(公告)日：1997-12-11
申请号：PCT/JP1997001937
申请日：1997-06-06
申请人： SONY CINEMA PRODUCTS CORPORATION , TACHI, Katsuichi
发明人： SONY CINEMA PRODUCTS CORPORATION
IPC分类号： H03L07/08
CPC分类号： H03L7/0891
摘要： A phase locked loop circuit which follows up the phase of an input signal is provided with a phase comparator (150) which compares the phase of an inputted reference signal with that of the input signal inputted as a comparison object synchronously with a prescribed operation clock. Therefore, first and second detecting sections (154 and 155) and JK flip-flops (162 and 163) output data in accordance with the operation clock, and hence the phase shift between NU and ND data based on the difference between the delay amount of each input data by a loop or feedback constituting part and the phase shift between two tri-state logic outputs are eliminated. Since the phase comparison between the inputted two signals, namely between the reference signal and input signal is performed synchronously with the operation clock, the comparison data obtained as a result of the phase comparison is outputted at prescribed time intervals. Therefore, the malfunction of the phase locked loop circuit is reduced as a whole.
摘要翻译：一个跟随输入信号相位的锁相环电路设置有相位比较器（150），它将输入的参考信号的相位与作为比较对象输入的输入信号的相位与规定的操作时钟同步进行比较。因此，第一和第二检测部分（154和155）和JK触发器（162和163）根据操作时钟输出数据，因此基于在NU和ND数据的延迟量消除了由循环或反馈构成部分的每个输入数据以及两个三态逻辑输出之间的相移。由于输入的两个信号之间，即参考信号和输入信号之间的相位比较与操作时钟同步地执行，所以作为相位比较的结果获得的比较数据以规定的时间间隔被输出。因此，整体上减小了锁相环电路的故障。

2. 发明申请

WO1997049084A1 SYNCHRONOUS CONTROLLER 审中-公开
标题翻译：同步控制器
公开(公告)号：WO1997049084A1
公开(公告)日：1997-12-24
申请号：PCT/JP1997002084
申请日：1997-06-17
申请人： SONY CINEMA PRODUCTS CORPORATION , IMAHASHI, Kazuyasu , TACHI, Katsuichi , NOGUCHI, Norihiko
发明人： SONY CINEMA PRODUCTS CORPORATION
IPC分类号： G11B20/10
CPC分类号： G03B31/00 , G11B27/10
摘要： A synchronous controller comprising a memory (101) in which blocked data are stored, a clock generating circuit (102) which generates an input-side clock (Cin) in accordance with the rate of data to be synchronized and a memory control circuit (103) which generates an output-side clock (Cout) in accordance with the input-side clock (Cin) from the clock generating circuit (102). The block-data are stored in the memory (101) in accordance with the input-side clock (Cin) and the stored blocked data are outputted from the memory (101) in units of a block in accordance with the output-side clock (Cout) from the memory control circuit (103). The difference between the quantity of the data inputted to the memory (101) and the quantity of the data outputted from the memory (101) is detected by the memory control circuit (103) and the speed of the output-side clock (Cout) is changed by the memory control circuit (103) in accordance with the detected differential quantity so as to be synchronized with the input-side clock (Cin) from the clock generating circuit.
摘要翻译：一种同步控制器，包括存储有阻塞数据的存储器（101），根据要同步的数据速率产生输入侧时钟（Cin）的时钟发生电路（102）和存储器控制电路（103 ），其根据来自时钟发生电路（102）的输入侧时钟（Cin）产生输出侧时钟（Cout）。块数据根据输入侧时钟（Cin）被存储在存储器（101）中，并且存储的阻塞数据以块的单位从存储器（101）输出，根据输出侧时钟 Cout）从存储器控制电路（103）发送。输入到存储器（101）的数据量与从存储器（101）输出的数据量之间的差异由存储器控制电路（103）和输出侧时钟（Cout）的速度检测，根据检测到的差分量由存储器控制电路（103）改变，以便与来自时钟发生电路的输入侧时钟（Cin）同步。

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