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1. 发明申请

WO2007010298A1 SIGMA DELTA MODULATORS 审中-公开
标题翻译： SIGMA DELTA调制器
公开(公告)号：WO2007010298A1
公开(公告)日：2007-01-25
申请号：PCT/GB2006/050175
申请日：2006-06-29
申请人： QUEEN MARY & WESTFIELD COLLEGE , SANDLER, Mark Brian , REISS, Joshua Daniel
发明人： SANDLER, Mark Brian , REISS, Joshua Daniel
IPC分类号： H03M3/00 , H03M7/32 , H03M7/36
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
摘要： A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behaviour has been observed, and major changes to design are not normally required to implement the detection mechanism.
摘要翻译：提供了一种用于检测具有在一系列时间间隔上变化的输出信号的Σ-Δ调制器中的极限周期的方法。在该方法中，将指示预定时间间隔之后的调制器输出信号的电平的第一值存储在第一存储器中，以及指示后续时间间隔之后的调制器输出信号电平的第二值到预定时间间隔被存储在第二存储器中。存储在第一存储器中的第一值与存储在第二存储器中的第二值进行比较，并且响应于这种比较，提供表示在调制器输出信号中产生极限周期趋势的输出。这种方法对于在Σ-Δ调制器中检测极限循环特别有利，因为它可以以直接的方式实现并提供非常精确的极限循环检测机制。因此，仅当观察到极限循环行为时才需要激活极限循环去除机构，并且通常不需要对设计的主要改变来实现检测机制。

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