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    • 1. 发明申请
    • INTEGRATED CIRCUIT WITH ESD PROTECTION UNIT
    • 集成电路与ESD保护单元
    • WO2010122496A1
    • 2010-10-28
    • PCT/IB2010/051731
    • 2010-04-20
    • NXP B.V.RUTH, ScottNEGOI, Andy, Catalin
    • RUTH, ScottNEGOI, Andy, Catalin
    • H01L27/02H03K19/003
    • H01L27/0266
    • An integrated circuit is provided which comprises an integrated circuit core unit (ICC), a plurality of input-output cells (IOC) coupled to the integrated circuit core unit (ICC) for protecting the core unit (ICC) from electrostatic discharges and a plurality of trigger units (TU). The integrated circuit furthermore comprises a first and second supply line (OVSS, OVDD), a first line (ESD boost) coupled to the trigger unit (TU), a second line (ESD trigger) coupled between the trigger unit (TU) and the at least one of the input-output cells (IOC), and a third line (esd_trigger_pmos). Each input-output cell (IOC) is coupled between the first and second supply line (OVSS, OVDD) and comprises a clamp transistor unit (CTN, CTP) coupled between the first and second supply line (OVSS, OVDD). The clamp transistor unit (CTN, CTP) can be implemented as a stacked complementary MOS unit with a series arrangement of a PMOS and a NMOS transistor. The trigger unit (TU) is coupled to the clamp transistor unit (CTN, CTP) via the second line (ESD_trigger). The trigger unit (TU) triggers the clamp transistor (CTN, CTP) via the second line (ESD trigger) if an electrostatic discharge is detected on the first line (OVSS).
    • 提供一种集成电路,其包括集成电路核心单元(ICC),耦合到用于保护核心单元(ICC)免受静电放电的集成电路核心单元(ICC)的多个输入输出单元(IOC)和多个 的触发单元(TU)。 集成电路还包括耦合到触发单元(TU)的第一和第二供电线(OVSS,OVDD),第一线(ESD升压),耦合在触发单元(TU)和第二线 至少一个输入 - 输出单元(IOC)和第三行(esd_trigger_pmos)。 每个输入输出单元(IOC)耦合在第一和第二电源线(OVSS,OVDD)之间,并且包括耦合在第一和第二电源线(OVSS,OVDD)之间的钳位晶体管单元(CTN,CTP)。 钳位晶体管单元(CTN,CTP)可以实现为具有PMOS和NMOS晶体管的串联布置的堆叠互补MOS单元。 触发单元(TU)通过第二线(ESD_trigger)耦合到钳位晶体管单元(CTN,CTP)。 如果在第一行(OVSS)上检测到静电放电,触发单元(TU)将通过第二行(ESD触发)触发钳位晶体管(CTN,CTP)。
    • 3. 发明申请
    • DISPLAY DEVICE HAVING REDUCED POWER CONSUMPTION
    • 具有降低功耗的显示设备
    • WO2005017869A1
    • 2005-02-24
    • PCT/IB2004/051411
    • 2004-08-06
    • KONINKLIJKE PHILIPS ELECTRONICS N. V.NEGOI, Andy CatalinPILLOUD, Bernard
    • NEGOI, Andy CatalinPILLOUD, Bernard
    • G09G3/36
    • G09G3/3625G09G3/3681G09G3/3692G09G3/3696G09G2330/023
    • The present invention concerns generally passive matrix displays, in particular a device comprising a display arrangement (1) and a display driver circuit (2). The display arrangement (1) comprises a liquid crystal material between a first substrate provided with row electrodes (7) and a second substrate provided with column electrodes (6), in which overlapping parts of the row and column electrodes define pixels (8). The display driver circuit (2) comprises means (5) for driving the column electrodes (6) and means (4) for driving the row electrodes (7). The row electrodes (7) supply groups of p rows (p>=2) with row selection voltage levels (V3, VC, MV3) for selecting rows and the column voltage levels (V2, V1, VC, MV1, MV2) are provided by means (5) for driving the column electrodes (6). The column voltage levels (V2, V1, VC, MV1, MV2) to be supplied to the column electrodes (6) are selectable from p+l different column voltage levels (V2, V1, VC, MV1, MV2) depending on the image data to be displayed, wherein the column voltage levels (V2, V1, VC, MV1, MV2) are symmetrically distributed around a middle voltage level (VC). To provide a display device having a low power consumption it is proposed to connect the middle voltage level (VC) in dependency on a deviation from a predetermined value of the middle voltage level (VC) with a higher (Vsupplyl) or a lower voltage potential (VSS) until the predetermined value of the middle voltage level (VC) is reached or the middle voltage level (VC) stays within a tolerance range.
    • 本发明一般涉及无源矩阵显示器,特别是包括显示装置(1)和显示驱动电路(2)的装置。 显示装置(1)包括在设置有行电极(7)的第一基板和设置有列电极(6)的第二基板之间的液晶材料,其中行电极和列电极的重叠部分限定像素(8)。 显示驱动电路(2)包括用于驱动列电极(6)的装置(5)和用于驱动行电极(7)的装置(4)。 行电极(7)提供具有用于选择行的行选择电压电平(V3,VC,MV3)的p行组(p> = 2),并且提供列电压电平(V2,V1,VC,MV1,MV2) 通过用于驱动列电极(6)的装置(5)。 根据图像,可以从p + 1个不同的列电压电平(V2,V1,VC,MV1,MV2)中选择要提供给列电极(6)的列电压电平(V2,V1,VC,MV1,MV2) 要显示的数据,其中列电压电平(V2,V1,VC,MV1,MV2)围绕中间电压电平(VC)对称分布。 为了提供具有低功耗的显示装置,建议根据具有较高(Vsupply1)或较低电压电位的中间电压电平(VC)的预定值的偏差来连接中间电压电平(VC) (VSS),直到达到中间电压电平(VC)的预定值或中间电压电平(VC)保持在公差范围内。