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1. 发明申请

WO2010078187A3 STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS 审中-公开
公开(公告)号：WO2010078187A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/069384
申请日：2009-12-23
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu S. , BISWAS, Arijit , RAASSCH, Steven , RACUNAS, Paul
发明人： MUKHERJEE, Shubhendu S. , BISWAS, Arijit , RAASSCH, Steven , RACUNAS, Paul
IPC分类号： G06F15/163 , G06F9/06 , G06F9/46 , G06F3/06
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.

2. 发明申请

WO2010078187A2 STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS 审中-公开
标题翻译：用于同步冗余处理器的状态存储
公开(公告)号：WO2010078187A2
公开(公告)日：2010-07-08
申请号：PCT/US2009069384
申请日：2009-12-23
申请人： INTEL CORP , MUKHERJEE SHUBHENDU S , BISWAS ARIJIT , RAASSCH STEVEN , RACUNAS PAUL
发明人： MUKHERJEE SHUBHENDU S , BISWAS ARIJIT , RAASSCH STEVEN , RACUNAS PAUL
IPC分类号： G06F15/163 , G06F3/06 , G06F9/06 , G06F9/46
CPC分类号： G06F15/16 , G06F11/1407 , G06F11/1641 , G06F11/1658 , G06F11/1683 , G06F11/1691
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
摘要翻译：公开了使用状态历史来同步冗余处理器的发明的实施例。在一个实施例中，装置包括两个处理器，每个处理器的状态存储器和控制逻辑。每个处理器都要执行相同的指令。状态存储器是存储由处理器执行的每个指令的压缩处理器状态信息。控制逻辑是基于来自状态存储器的条目来同步两个处理器。

3. 发明申请

WO2006012284A2 AN APPARATUS AND METHOD FOR PACKET COALESCING WITHIN INTERCONNECTION NETWORK ROUTERS 审中-公开
标题翻译：在互连网络路由器中分组分组的装置和方法
公开(公告)号：WO2006012284A2
公开(公告)日：2006-02-02
申请号：PCT/US2005/022446
申请日：2005-06-24
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu, S.
发明人： MUKHERJEE, Shubhendu, S.
IPC分类号： G06F12/08
CPC分类号： G06F15/17375
摘要： A method and apparatus for packet coalescing within interconnection network routers. In one embodiment, the method includes the scan of at least one input buffer to identify at least two network packets that include coherence protocol messages and are directed to the same destination, but from different sources. In one embodiment, coherence protocol messages within the network packets are combined into a coalesced network packet. Once combined, the coalesced network packet is transmitted to the same or matching destination. In one embodiment, combining multiple network packets (each containing a single logical coherence message) into a larger, coalesced network packet amortizes the fixed overhead of sending a network packet including a single coherence message, as compared to the larger, coalesced network packet, to improve bandwidth usage. Other embodiments are described and claimed.
摘要翻译：用于互连网络路由器内的分组聚合的方法和装置。在一个实施例中，该方法包括扫描至少一个输入缓冲器以识别包括相干协议消息并且被引导到相同目的地但是来自不同来源的至少两个网络分组。在一个实施例中，网络分组内的相干协议消息被组合成合并的网络分组。一旦组合，合并的网络分组被发送到相同或匹配的目的地。在一个实施例中，将多个网络分组（每个包含单个逻辑相干消息）组合到更大的合并网络分组中，将与包括较大的合并网络分组相比的包括单个相干消息的网络分组的固定开销分摊到提高带宽使用率。描述和要求保护其他实施例。

4. 发明申请

WO2007005818A3 REDUCING THE UNCORRECTABLE ERROR RATE IN A LOCKSTEPPED DUAL-MODULAR REDUNDANCY SYSTEM 审中-公开
标题翻译：减少锁定双模块冗余系统中的不正确的错误率
公开(公告)号：WO2007005818A3
公开(公告)日：2007-05-10
申请号：PCT/US2006025959
申请日：2006-06-29
申请人： INTEL CORP , RACUNAS PAUL B , EMER JOEL S , BISWAS ARIJIT , MUKHERJEE SHUBHENDU S , RAASCH STEVEN E
发明人： RACUNAS PAUL B , EMER JOEL S , BISWAS ARIJIT , MUKHERJEE SHUBHENDU S , RAASCH STEVEN E
IPC分类号： G06F11/16
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1658 , G06F11/1683
摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
摘要翻译：公开了用于降低锁定双模块冗余系统中的不可校正错误率的装置和方法的实施例。在一个实施例中，装置包括两个处理器核，微检查器，全局检验器和故障逻辑。微检查器是检测来自一个核心中的结构的值是否与另一个核心中的相应结构的值匹配。全局检查器是检测两个内核之间的锁步失败。如果存在锁步错误但微检查器检测到不匹配，则故障逻辑是使两个内核重新同步。

5. 发明申请

WO2007005818A2 REDUCING THE UNCORRECTABLE ERROR RATE IN A LOCKSTEPPED DUAL-MODULAR REDUNDANCY SYSTEM 审中-公开
标题翻译：降低失锁双模冗余系统中的不可纠错误率
公开(公告)号：WO2007005818A2
公开(公告)日：2007-01-11
申请号：PCT/US2006/025959
申请日：2006-06-29
申请人： INTEL CORPORATION , RACUNAS, Paul, B. , EMER, Joel, S. , BISWAS, Arijit , MUKHERJEE, Shubhendu, S. , RAASCH, Steven, E.
发明人： RACUNAS, Paul, B. , EMER, Joel, S. , BISWAS, Arijit , MUKHERJEE, Shubhendu, S. , RAASCH, Steven, E.
CPC分类号： G06F11/165 , G06F11/1641 , G06F11/1658 , G06F11/1683
摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
摘要翻译：公开了用于减少锁步双模冗余系统中的不可纠正错误率的装置和方法的实施例。在一个实施例中，一种设备包括两个处理器核心，微检查器，全局检查器和故障逻辑。微检查器将检测来自一个内核中的结构的值是否与来自另一个内核中的对应结构的值匹配。全局检查器将检测两个内核之间的锁步故障。如果存在锁步错误，但微检查器检测到不匹配，则故障逻辑将导致两个内核重新同步。

6. 发明申请

WO2005066784A1 BUFFERING UNCHECKED STORES FOR FAULT DETECTION IN REDUNDANT MULTITHREADING SYSTEMS USING SPECULATIVE MEMORY SUPPORT 审中-公开
标题翻译：在使用分析性记忆支持的情况下，减少冗余多用户系统故障检测的仓库
公开(公告)号：WO2005066784A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043685
申请日：2004-12-23
申请人： INTEL CORPORATION , REINHARDT, Steven, K. , MUKHERJEE, Shubhendu, S. , EMER, Joel, S. , WEAVER, Christopher, T.
发明人： REINHARDT, Steven, K. , MUKHERJEE, Shubhendu, S. , EMER, Joel, S. , WEAVER, Christopher, T.
IPC分类号： G06F11/14
CPC分类号： G06F11/1497
摘要： A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.
摘要翻译：公开了一种多线程架构，用于使用推测性内存支持在冗余多线程系统中缓存未检查的存储以进行故障检测。特别地，SRT处理器的性能通过使用推测性内存支持来缓冲领先的线程存储来增强，直到它们可以与其尾随线程对应来进行比较。将这些存储缓冲在存储器系统中，可以将它们从存储缓冲区中删除。由于推测性内存系统的容量会比存储缓冲区大，所以可能会在引导线程被迫停止之前缓存附加存储。这将导致线程之间的松弛增加，从而导致性能的提高。

7. 发明申请

WO2006012284A3 AN APPARATUS AND METHOD FOR PACKET COALESCING WITHIN INTERCONNECTION NETWORK ROUTERS 审中-公开
标题翻译：在互连网络路由器中分组分组的装置和方法
公开(公告)号：WO2006012284A3
公开(公告)日：2007-01-25
申请号：PCT/US2005022446
申请日：2005-06-24
申请人： INTEL CORP , MUKHERJEE SHUBHENDU S
发明人： MUKHERJEE SHUBHENDU S
IPC分类号： G06F15/173
CPC分类号： G06F15/17375
摘要： A method and apparatus for packet coalescing within interconnection network routers. In one embodiment, the method includes the scan of at least one input buffer to identify at least two network packets that include coherence protocol messages and are directed to the same destination, but from different sources. In one embodiment, coherence protocol messages within the network packets are combined into a coalesced network packet. Once combined, the coalesced network packet is transmitted to the same or matching destination. In one embodiment, combining multiple network packets (each containing a single logical coherence message) into a larger, coalesced network packet amortizes the fixed overhead of sending a network packet including a single coherence message, as compared to the larger, coalesced network packet, to improve bandwidth usage. Other embodiments are described and claimed.
摘要翻译：一种用于互连网络路由器内的分组聚合的方法和装置。在一个实施例中，该方法包括扫描至少一个输入缓冲器以识别包括相干协议消息并且被引导到相同目的地但是来自不同来源的至少两个网络分组。在一个实施例中，网络分组内的相干协议消息被组合成合并的网络分组。一旦组合，将合并的网络分组发送到相同或匹配的目的地。在一个实施例中，将多个网络分组（每个包含单个逻辑相干消息）组合到更大的合并网络分组中，将与包括较大的合并网络分组相比的包括单个相干消息的网络分组的固定开销分摊到提高带宽使用率。描述和要求保护其他实施例。

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