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1. 发明申请

WO1997014103A1 MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：多处理器系统
公开(公告)号：WO1997014103A1
公开(公告)日：1997-04-17
申请号：PCT/JP1995002105
申请日：1995-10-13
申请人： HITACHI, LTD. , TAKEWA, Hidehito , MORIOKA, Michio , KOKURA, Shin , KUROSAWA, Kenichi , FUKUNAKA, Hidetada
发明人： HITACHI, LTD.
IPC分类号： G06F15/16
CPC分类号： G06F9/52 , G06F13/1631
摘要： A high performance multiprocessor system in which coherency maintenance, though done by a memory control chip and a processor in the prior art, is carried out by a memory control chip alone, thereby reducing processor load and improving bus efficiency. Coherency maintenance is executed by conflict detection means (128) for detecting coincidence between a reference address of read request from a processor (104, 105, 106, 107) and a reference address of write request generated later from another processor than the read request, and monitoring the end of coherent report for the read request; control means (114) for judging that the write data of the write request is the read data of the read request from this detection result and the end result; and a retry read buffer (132) for repeating a memory read operation by using the address of the read request after the write request has been fulfilled according to this judgement result.
摘要翻译：一种高性能多处理器系统，其中虽然由存储器控制芯片和现有技术中的处理器完成的一致性维护仅由存储器控制芯片执行，从而减少处理器负载并提高总线效率。一致性维护由冲突检测装置（128）执行，用于检测来自处理器（104,105,106,107）的读取请求的参考地址与稍后从另一个处理器产生的读取请求之间的写入请求的参考地址之间的一致性，并监视读取请求的连贯报告的结束; 控制装置（114），用于根据该检测结果和最终结果判断写入请求的写入数据是读取请求的读取数据; 以及重试读缓冲器（132），用于根据该判断结果，在写请求已经满足之后通过使用读请求的地址重复存储器读操作。

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