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1. 发明申请

WO2016073904A1 COUPLING ON-DIE INDUCTORS FOR RADIO-FREQUENCY APPLICATIONS 审中-公开
标题翻译：用于无线电频率应用的耦合式电感电感器
公开(公告)号：WO2016073904A1
公开(公告)日：2016-05-12
申请号：PCT/US2015/059552
申请日：2015-11-06
申请人： MORFIS SEMICONDUCTOR, INC.
发明人： LI, Haitao , LUO, Sifen , CHEN, Changli
IPC分类号： H01P5/18
CPC分类号： H01F17/0006 , H01F2017/0046
摘要： A circuit includes a dielectric layer, a first via residing in the dielectric layer, a second via residing in the dielectric layer, and an inductor. The inductor includes a first inductor element and a second inductor element. The first inductor element is formed by a first transmission line including a plurality of segments defined between a first end and a second end thereof. The second inductor element is formed by a second transmission line including a plurality of segments defined between a first end and a second end thereof. A first port is defined by one segment of the plurality of segments of the second transmission line, wherein current flows in the inductor in the same direction from the second port defined at the first end of the first transmission line to the first port, and from the first port to a third port defined at the second via.
摘要翻译：电路包括电介质层，驻留在电介质层中的第一通孔，位于电介质层中的第二通道和电感器。电感器包括第一电感器元件和第二电感器元件。第一电感器元件由包括限定在其第一端和第二端之间的多个段的第一传输线形成。第二电感器元件由包括限定在其第一端和第二端之间的多个段的第二传输线形成。第一端口由第二传输线的多个段的一个段限定，其中，电流在与第一传输线的第一端限定的第二端口相同的方向上流向第一端口，并且从在第二个通道上定义的第一个端口到第三个端口。

2. 发明申请

WO2016073766A1 LAMINATE RF CHOKE FOR FLIP-CHIP POWER AMPLIFIER 审中-公开
标题翻译：层压RF选择片式功率放大器
公开(公告)号：WO2016073766A1
公开(公告)日：2016-05-12
申请号：PCT/US2015/059307
申请日：2015-11-05
申请人： MORFIS SEMICONDUCTOR, INC.
发明人： LI, Haitao , CHEN, Changli
IPC分类号： H01L23/64 , H01L23/50 , H01L33/48
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a flip-chip die and a laminate substrate. The flip-chip die includes a first bump and a second bump. A first metal layer is disposed on the laminate substrate. The first metal layer includes a first transmission line having a plurality of segments forming a first spiral inductor. A first end of the first transmission line is electrically coupled to the first bump. A second end of the first transmission line is electrically coupled to a first power supply pin.
摘要翻译：电路包括倒装芯片和层叠基板。倒装芯片包括第一凸块和第二凸块。第一金属层设置在层叠基板上。第一金属层包括具有形成第一螺旋电感器的多个段的第一传输线。第一传输线的第一端电连接到第一凸块。第一传输线的第二端电耦合到第一电源引脚。

3. 发明申请

WO2016073784A1 BIAS-BOOSTING CIRCUIT WITH DUAL CURRENT MIRRORS FOR RF POWER AMPLIFIER 审中-公开
标题翻译：用于射频功率放大器的双电流镜的偏置电路
公开(公告)号：WO2016073784A1
公开(公告)日：2016-05-12
申请号：PCT/US2015/059330
申请日：2015-11-05
申请人： MORFIS SEMICONDUCTOR, INC.
发明人： LUO, Sifen , CHEN, Changli
IPC分类号： H03F1/02 , H03F1/30 , H03F3/19
CPC分类号： H03F3/193 , H03F1/0261 , H03F1/223 , H03F1/565 , H03F3/245 , H03F2200/18 , H03F2200/451 , H03F2200/555
摘要： An RF power amplifier circuit has a signal input and a signal output. An input matching network connected to the signal input, and an output matching network is connected to the signal output. There is a power amplifier with an input connected to the input matching network, and an output connected to the output matching network. A bias boosting circuit is connected to the input of the power amplifier, and the bias boosting circuit comprises a cascode current mirror that is defined by a first cascode circuit and a second cascode circuit, and a biasing transistor that is connected to an output of the cascode current mirror. The biasing transistor, together with the power amplifier, defines a current mirror. The bias boosting circuit is thus a dual current mirror circuit that boosts the bias of the power amplifier.
摘要翻译： RF功率放大器电路具有信号输入和信号输出。连接到信号输入的输入匹配网络和输出匹配网络连接到信号输出。有一个功率放大器，其输入端连接到输入匹配网络，输出端连接到输出匹配网络。偏置升压电路连接到功率放大器的输入，偏压升压电路包括由第一共源共栅电路和第二共源共栅电路限定的共源共栅电流镜，以及连接到共源共栅电流镜。偏置晶体管与功率放大器一起定义电流镜。因此，偏压升压电路是提高功率放大器偏压的双电流镜电路。

4. 发明申请

WO2016168736A1 BIAS-BOOSTING CIRCUIT WITH A MODIFIED WILSON CURRENT MIRROR CIRCUIT FOR RADIO FREQUENCY POWER AMPLIFIERS 审中-公开
标题翻译：用于无线电频率功率放大器的改进型威尔逊电流镜电路的偏压升压电路
公开(公告)号：WO2016168736A1
公开(公告)日：2016-10-20
申请号：PCT/US2016/027941
申请日：2016-04-15
申请人： MORFIS SEMICONDUCTOR, INC.
发明人： LUO, Sifen , XU, Zhan , CHEN, Changli , LI, Haitao , CHANG, Heng-Chia , WANG, Narisi , YOON, Jung Ho
IPC分类号： H03F3/04 , H03F3/191 , H03F3/42
CPC分类号： H03F3/213 , H03F1/0205 , H03F1/0261 , H03F1/223 , H03F1/3205 , H03F3/195 , H03F3/245 , H03F2200/18 , H03F2200/451
摘要： A current mirror circuit for biasing a power amplifier includes a modified Wilson current mirror with a pair of first and second mirror transistors connected to a third transistor. The first mirror transistor is configured for operating in a saturation mode, with a gate voltage of the first mirror transistor being lower than a gate voltage of the power amplifier. The third transistor charges the power amplifier circuit during a positive half cycle of an input signal and the first mirror transistor discharges the power amplifier circuit during a negative half cycle of the input signal at different rates.
摘要翻译：用于偏置功率放大器的电流镜电路包括修改的威尔逊电流镜，其具有连接到第三晶体管的一对第一和第二反射镜晶体管。第一镜晶体管被配置为在饱和模式下工作，其中第一镜晶体管的栅极电压低于功率放大器的栅极电压。第三晶体管在输入信号的正半周期期间对功率放大器电路进行充电，并且第一反射镜晶体管在输入信号的负半周期内以不同的速率放电功率放大器电路。

5. 发明申请

WO2016073624A1 MULTI-LAYER TRANSMISSION LINE STRUCTURE FOR MISALIGNMENT RELIEF 审中-公开
标题翻译：用于MISALIGNMENT RELIEF的多层传输线结构
公开(公告)号：WO2016073624A1
公开(公告)日：2016-05-12
申请号：PCT/US2015/059062
申请日：2015-11-04
申请人： MORFIS SEMICONDUCTOR, INC.
发明人： LI, Haitao
IPC分类号： H01F5/00
CPC分类号： H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a dielectric layer and a stacked inductor. A first metal line is disposed on a first side of the dielectric layer. A second metal line is disposed on a second side of the dielectric layer and inductively coupled with the first metal line through a portion of the dielectric layer. The first metal line has a first width between respective edges of the first metal line. The second metal line has a second width between respective edges of the second metal line. The second width of the second metal line is greater than the first width of the first metal line. The first metal line is vertically aligned with the second metal line. The respective edges of the second metal line are located outwardly of the respective edges of the first metal line.
摘要翻译：电路包括电介质层和层叠电感器。第一金属线设置在电介质层的第一侧上。第二金属线设置在电介质层的第二侧上，并通过电介质层的一部分与第一金属线感应耦合。第一金属线在第一金属线的相应边缘之间具有第一宽度。第二金属线在第二金属线的相应边缘之间具有第二宽度。第二金属线的第二宽度大于第一金属线的第一宽度。第一金属线与第二金属线垂直对准。第二金属线的相应边缘位于第一金属线的相应边缘的外侧。

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