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    • 6. 发明申请
    • INTEGRATED ETHERNET SWITCH
    • 集成以太网交换机
    • WO0106692A3
    • 2001-06-07
    • PCT/US0008637
    • 2000-03-31
    • BROADCOM CORPHAO YI HSIENMCDANIEL SCOTTLENELL JOHN KNAYLOR ANDREW M
    • HAO YI-HSIENMCDANIEL SCOTTLENELL JOHN KNAYLOR ANDREW M
    • H04L12/56H04L12/44
    • H04L49/351H04L49/103H04L49/254H04L49/30H04L49/45
    • A network switch having PHY integrated with the switch. The switch also integrates MAC with PHY. The PHY, MAC, and switch are integrated onto a single VLSI component. The network switch implements an IEEE Standard 802.3 communication protocol which may include autonegotiation, flow control, and duplexing. The communication protocol can include a 10Base-T communication protocol and a 100Base-T communication protocol. The switch includes an Address Resolution Table using associative memory. A free buffer pool, Transmit Descriptor Table, a Packet Storage Table, and combinations thereof also may reside with the Address Resolution Table in a shared memory block. Each PHY/MAC pair in the switch employs only a single Link Partner Capability Register. The switch uses a common system clock which is driven by a single clock source. The PLL that drives the PHY also drives the switch functions through a first clock generator. A second clock generator is used to drive devices external to the switch, such as memory.
    • 具有与交换机集成的PHY的网络交换机。 该交换机还集成了MAC与PHY。 PHY,MAC和交换机集成到单个VLSI组件上。 网络交换机实现IEEE标准802.3通信协议,其可以包括自动协商,流量控制和双工。 通信协议可以包括10Base-T通信协议和100Base-T通信协议。 交换机包括使用关联存储器的地址解析表。 空闲缓冲池,传输描述符表,分组存储表及其组合也可以与共享存储器块中的地址解析表一起存在。 交换机中的每个PHY / MAC对仅使用单个链路伙伴能力寄存器。 交换机使用由单个时钟源驱动的公共系统时钟。 驱动PHY的PLL还通过第一个时钟发生器驱动开关功能。 第二个时钟发生器用于驱动交换机外部的设备,如存储器。